Jin-Ku Kang

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 30

Top Topics

Pruning Methods

Frequency Modulation

Top Venues

IEICE Electron. Express

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Hyunjun Ko, Jin-Ku Kang, Yongwoo Kim
An Efficient and Fast Filter Pruning Method for Object Detection in Embedded Systems. AICAS (2024)
Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim
Fast, Efficient and Lightweight Compressed Image Super-Resolution Network for Edge Devices. AICAS (2024)
Jaemyung Kim, Hyun-Ho Kim, Doo-Chun Seo, Jae-Heon Jeong, Jin-Ku Kang, Yongwoo Kim
MASCAR: Multidomain Adaptive Spatial-Spectral Variable Compression Artifact Removal Network for Multispectral Remote Sensing Images. IEEE Trans. Geosci. Remote. Sens. 62 (2024)
Yong-Sung Ahn, Jeong-Mi Park, Jin-Ku Kang, Jaehoon Jun
A ±0.48°C (3σ) Inaccuracy BJT-Based Temperature Sensor With 241 μs Conversion Time for Display Driver IC in 40 nm CMOS. IEEE Access 11 (2023)
Jeong-Mi Park, Jin-Ku Kang
A PAM-4 Receiver with Selective Reference Voltage Adaptation for Low Sensitivity to Sampler Voltage Variations. ISOCC (2023)
Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim
An FPGA-based Lightweight Deblocking CNN for Edge Devices. ISCAS (2023)
Seoung-Geun Cho, Jin-Ku Kang
A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler. ISOCC (2023)
Jin-Ho Kim, Jin-Ku Kang
A Wide-range Low Power Quarter Rate Single Loop CDR. ISOCC (2022)
Jihun Jeon, Jin-Ku Kang, Yongwoo Kim
Filter Pruning Method for Inference Time Acceleration Based on YOLOX in Edge Device. ISOCC (2022)
Jihun Jeon, Jaemyung Kim, Jin-Ku Kang, Sungtae Moon, Yongwoo Kim
Target Capacity Filter Pruning Method for Optimized Inference Time Based on YOLOv5 in Embedded Systems. IEEE Access 10 (2022)
Jaepil Bak, Taek-Joon An, Youngwoo Kim, Jin-Ku Kang
An Overhead-Reduced Key Coding Technique for High-Speed Serial Interface. IEEE Access 10 (2022)
Sang-Ung Shin, Jin-Ku Kang, Yongwoo Kim
A Design and Implementation of MIPI A-PHY RTS Layer. ISOCC (2022)
Hwan-Ung Kim, Jin-Ku Kang
High-speed Serial Interface using PWAM Signaling Scheme. ISOCC (2022)
Hyun-In Kim, Jin-Ku Kang
A Low-Power Counter-based Digital CDR. ISOCC (2022)
Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim
An FPGA Implementation of CNN-based Compression Artifact Reduction. ISOCC (2022)
Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim
A Low-Cost Fully Integer-Based CNN Accelerator on FPGA for Real-Time Traffic Sign Recognition. IEEE Access 10 (2022)
Kyeong-Min Ko, Dohyeon Kwon, Jin-Ku Kang
Design of 20Gb/s PAM4 Transmitter with Maximum Transition Elimination and Transition Compensation Techniques. ISOCC (2021)
Jaemyung Kim, Jin-Ku Kang, Yongwoo Kim
A Resource Efficient Integer-Arithmetic-Only FPGA-Based CNN Accelerator for Real-Time Facial Emotion Recognition. IEEE Access 9 (2021)
Hyung-Wook Lee, Kyeong-Min Ko, Jin-Ku Kang
An 8 - 26 Gb/s Single Loop Reference-less CDR with Unrestricted Frequency Acquisition. ISOCC (2021)
Nguyen Huu Tho, Ho-Joon Lee, Taek-Joon An, Jin-Ku Kang
A 0.32-2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition. IEEE Trans. Circuits Syst. II Express Briefs 68 (7) (2021)
Chang han Rho, Jin-Ku Kang, Jin Liu
Two-step Time-to-Digital Converter using pulse-shifting time-difference repetition circuit. ISOCC (2021)
Kyung-Sub Son, Taek-Joon An, Yong-Hwan Moon, Jin-Ku Kang
A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition. IEEE Trans. Circuits Syst. II Express Briefs (6) (2020)
Kyung-Sub Son, Yong-Hwan Moon, Sanghun Baek, Namyong Kim, Taek-Joon An, Jin-Ku Kang
Eye-open monitor using two-dimensional counter value profile. IEICE Electron. Express 16 (21) (2019)
Yong-Hwan Moon, Jae-Wook Yoo, Young-Soo Ryu, Sang-Ho Kim, Kyung-Sub Son, Jin-Ku Kang
A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Seong-Mun An, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang
Design of a third-order delta-sigma TDC with error-feedback structure. IEICE Electron. Express 16 (3) (2019)
Min Kim, Kyung-Sub Son, Namhoon Kim, Chang Hang Rho, Jin-Ku Kang
A Two-Step Time-to-Digital Converter using Ring Oscillator Time Amplifier. ISOCC (2018)
Nguyen Huu Tho, Kyung-Sub Son, Jin-Ku Kang
A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector. IEICE Electron. Express 14 (8) (2017)
Bum-Hee Choi, Kyung-Sub Son, Jin-Ku Kang
A low jitter burst-mode clock and data recovery circuit with two symmetric VCO's. APCCAS (2016)
Bum-Hee Choi, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang
A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's. IEICE Electron. Express 13 (24) (2016)
Nguyen Huu Tho, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang
A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector. ISOCC (2016)
Hyun-Bae Jin, Gi-Yeol Bae, Kwang-Hee Yoon, Tae-Ho Kim, Ji-Hoon Jang, Byung Cheol Song, Jin-Ku Kang
A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing. J. Signal Process. Syst. 79 (1) (2015)
Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang
On-chip jitter tolerance measurement technique for CDR circuits. ISCAS (2015)
In-Seok Kong, Kyung-Sub Son, Kyongsu Lee, Jin-Ku Kang
Precise time-difference repetition for TDC with delay mismatch cancelling scheme. IEICE Electron. Express 12 (21) (2015)
Kyung-Sub Son, Jin-Ku Kang
On-chip jitter tolerance measurement technique with independent jitter frequency modulation from VCO in CDR. IEICE Electron. Express 12 (15) (2015)
Taek-Joon Ahn, Sang-Soon Im, Yong-Sung Ahn, Jin-Ku Kang
A low jitter clock and data recovery with a single edge sensing Bang-Bang PD. IEICE Electron. Express 11 (7) (2014)
Taek-Joon Ahn, Kyung-Sub Son, Yong-Sung Ahn, Jin-Ku Kang
A low-power CDR using dynamic CML latches and V/I converter merged with XOR for half-rate linear phase detection. IEICE Electron. Express 11 (17) (2014)
Hak Gu Kim, Jin-Ku Kang, Byung Cheol Song
Automatic SfM-Based 2D-to-3D Conversion for Multi-Object Scenes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2014)
Kyongsu Lee, Youngjin Kim, Kyung-Sub Son, Sangmin Lee, Jin-Ku Kang
A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS. IEICE Electron. Express 11 (17) (2014)
Yong-Hwan Moon, In-Seok Kong, Young-Soo Ryu, Jin-Ku Kang
A 2.2-mW 20-135-MHz False-Lock-Free DLL for Display Interface in 0.15-µm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (8) (2014)
Yong-Sung Ahn, Taek-Joon Ahn, Kyongsu Lee, Jin-Ku Kang
Avoiding noise frequency interference with binary phase pulse driving and CDS for capacitive TSP controller. IEICE Electron. Express 11 (21) (2014)
Taek-Joon An, Kyung-Sub Son, Young-Jin Kim, In-Seok Kong, Jin-Ku Kang
A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. ISCAS (2014)
Benjamin P. Wilkerson, Jin-Ku Kang
A low power BPSK demodulator for wireless implantable biomedical devices. ISCAS (2013)
Hak Gu Kim, Jin-Ku Kang, Byung Cheol Song
Three-dimensional perception improvement using sharpness adjustment and hardware implementation. ICME Workshops (2013)
Benjamin P. Wilkerson, Joon-Hyup Seo, Jin-Cheol Seo, Jin-Ku Kang
An ultra-low power BPSK demodulator with dual band filtering for implantable biomedical devices. IEICE Electron. Express 10 (7) (2013)
Jin-Cheol Seo, Sang-Soon Im, Kwan-Hee Yoon, Seung-Wook Oh, Taek-Joon An, Gi-Yeol Bae, Jin-Ku Kang
A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. SoCC (2012)
Seung-Wook Oh, Hyung-Min Park, Joon-Hyup Seo, Jae-Young Jang, Gi-Yeol Bae, Jin-Ku Kang
A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS. ISOCC (2012)
Benjamin P. Wilkerson, Jin-Ku Kang
A non-coherent BPSK receiver with dual band filtering for implantable biomedical devices. ICECS (2012)
Jin-Cheol Seo, Tae-Ho Kim, Taek-Joon An, Kwan Yoon, Jin-Ku Kang
A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern. ISOCC (2012)
Tae Hwan Lee, Jin-Ku Kang, Byung Cheol Song
Video denoising using overlapped motion compensation and advanced collaborative filtering. J. Electronic Imaging 21 (2) (2012)
Tae-Ho Kim, Jin-Cheol Seo, Yong-Sung Ahn, Jin-Ku Kang
A 10Gb/s adaptive equalizer with ISI level measurement. IEICE Electron. Express 9 (17) (2012)
Seung-Wuk Oh, Sang-Ho Kim, Jin-Ku Kang
An audio clock regenerator with a wide dividing ratio for HDMI. ISCAS (2012)
Tae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang
A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement. ESSCIRC (2011)
Sungjae Lee, Jin-Ku Kang, Inhwan Lee
Way-lookup buffer for low-power set-associative cache. IEICE Electron. Express 8 (23) (2011)
Benjamin P. Wilkerson, Tae-Ho Kim, Jin-Ku Kang
Low-power non-coherent data and power recovery circuit for implantable biomedical devices. ISOCC (2011)
Tae-Ho Kim, Yong-Hwan Moon, Jin-Ku Kang
A 4 Gb/s Adaptive FFE/DFE Receiver with a Data-Dependent Jitter Measurement. IEICE Trans. Electron. (11) (2011)
Tae-Ho Kim, Sang-Ho Kim, Jin-Ku Kang
A DLL-based Clock Data Recovery with a modified input format. IEICE Electron. Express 7 (8) (2010)
Sang-Ho Kim, Hyung-Min Park, Tae-Ho Kim, Jin-Ku Kang, Jin-Ho Kim, Jae-Youl Lee, Yoon-Kyung Choi, Myunghee Lee
A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS. SoCC (2010)
Hyung-Min Park, Hyun-Bae Jin, Jin-Ku Kang
SSCG with Hershey-Kiss modulation profile using Dual Sigma-Delta modulators. IEICE Electron. Express 7 (18) (2010)
Jae-Wook Yoo, Tae-Ho Kim, Dong-Kyun Kim, Jin-Ku Kang
A CMOS 5.4/3.24Gbps dual-rate clock and data recovery design for DisplayPort v1.2. SoCC (2010)
Seungwon Lee, Tae-Ho Kim, Jae-Wook Yoo, Jin-Ku Kang
A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS. SoCC (2009)
Yong-Woo Kim, Beomseok Shin, Jin-Ku Kang
High-speed 8B/10B encoder design using a simplified coding table. IEICE Electron. Express 5 (16) (2008)
Yong-Woo Kim, Jin-Ku Kang
An 8B/10B encoder with a modified coding table. APCCAS (2008)
Hyung-Wook Jang, Sung-Sop Lee, Jin-Ku Kang
A clock recovery circuit using half-rate 4×-oversampling PD. ISCAS (3) (2005)
Sung-Sop Lee, Hyung-Wook Jang, Jin-Ku Kang
3.125Gbps Reference-less Clock and Data Recovery using 4X Oversampling. SoCC (2005)
Chang-Hoon Lee, Seung-Ho Park, Jin-Ku Kang, Choon-Woo Kim
A real time image processor for reproduction of gray levels in dark areas on plasma display panel (PDP). IEEE Trans. Consumer Electron. 48 (4) (2002)
Jin-Ku Kang, Dong-Hee Kim
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. ISCAS (4) (2001)
Jin-Ku Kang, Wentai Liu, Ralph K. Cavin III
A CMOS high-speed data recovery circuit using the matched delay sampling technique. IEEE J. Solid State Circuits 32 (10) (1997)