Masato Iwabuchi

Publication Activity (10 Years)

Years Active: 1994-1999
Publications (10 Years): 0

Publications

Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design. ISPD (1999)
Mikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita
An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation. ASP-DAC (1995)
Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. IEEE J. Solid State Circuits 29 (4) (1994)