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A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates.
Masato Iwabuchi
Masami Usami
Masamori Kashiyama
Takashi Oomori
Shigeharu Murata
Toshiro Hiramoto
Takashi Hashimoto
Yasuhiro Nakajima
Published in:
IEEE J. Solid State Circuits (1994)
Keyphrases
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logic circuits
knowledge base
random access memory
classical logic
modal logic
multi valued
network simulator
neural network
low power
automated reasoning
defeasible logic
logic programming
data sets
nonmonotonic logics
general knowledge
predicate logic
formal theory