A 90-nm variable frequency clock system for a power-managed itanium architecture processor.
Tim FischerJayen DesaiBruce Andrew DoyleSamuel NaffzigerBen PatellaPublished in: IEEE J. Solid State Circuits (2006)
Keyphrases
- clock frequency
- power consumption
- cmos technology
- parallel architecture
- clock gating
- nm technology
- low power
- duty cycle
- high speed
- fpga device
- xilinx virtex
- multithreading
- power management
- multi processor
- power reduction
- parallel processing
- low voltage
- management system
- real time
- instruction set
- high end
- industry standard
- software architecture
- single chip
- computer architecture
- memory subsystem
- hardware implementation
- processing elements
- low cost
- computation intensive
- ibm zenterprise
- systolic array