3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU.
John J. WuuRahul AgarwalMichael CiraulaCarl DietzBrett JohnsonDave JohnsonRussell SchreiberRaja SwaminathanWill WalkerSamuel NaffzigerPublished in: ISSCC (2022)
Keyphrases
- cache misses
- memory hierarchy
- multithreading
- hit rate
- prefetching
- query processing
- shared memory multiprocessor
- cache management
- memory access
- computing power
- data access
- web caching
- replacement policy
- main memory
- hardware implementation
- access patterns
- back end
- garbage collection
- web documents
- data management
- hit ratio
- motion estimation
- caching scheme
- real time