Marios C. Papaefthymiou

Publication Activity (10 Years)

Years Active: 1991-2018
Publications (10 Years): 9

Top Topics

Top Venues

Publications

Parker Hill, Babak Zamirai, Shengshuo Lu, Yu-Wei Chao, Michael Laurenzano, Mehrzad Samadi, Marios C. Papaefthymiou, Scott A. Mahlke, Thomas F. Wenisch, Jia Deng, Lingjia Tang, Jason Mars
Rethinking Numerical Representations for Deep Neural Networks. CoRR (2018)
Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. ESSCIRC (2018)
Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. ISSCC (2017)
Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
AES core with DPA resistance for IoT devices. A-SSCC (2017)
Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (12) (2016)
Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
neural network engine with stream architecture and resonant clock mesh. A-SSCC (2016)
Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. VLSIC (2015)
Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. A-SSCC (2015)
Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. ASP-DAC (2015)
Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. ISSCC (2014)
Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits 48 (1) (2013)
Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
Computational sprinting on a hardware/software testbed. ASPLOS (2013)
Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
Designing for Responsiveness with Computational Sprinting. IEEE Micro 33 (3) (2013)
Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
Utilizing Dark Silicon to Save Energy with Computational Sprinting. IEEE Micro 33 (5) (2013)
Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. Very Large Scale Integr. Syst. 20 (6) (2012)
Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
Computational sprinting. HPCA (2012)
Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC (2012)
Wei-Hsiang Ma, Jerry C. Kao, Marios C. Papaefthymiou
A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. ESSCIRC (2011)
Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
187 MHz Subthreshold-Supply Charge-Recovery FIR. IEEE J. Solid State Circuits 45 (4) (2010)
Alexander T. Ishii, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
A resonant-clock 200MHz ARM926EJ-STM microcontroller. ESSCIRC (2009)
Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. ESSCIRC (2009)
Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
Resonant-Clock Latch-Based Design. IEEE J. Solid State Circuits 43 (4) (2008)
Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou
Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits 42 (1) (2007)
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs (7) (2007)
Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. CICC (2007)
Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power CoRR (2007)
Zhengtao Yu, Marios C. Papaefthymiou, Xun Liu
Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI (2007)
Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves
Parallelizing post-placement timing optimization. IPDPS (2006)
Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC (2006)
Xun Liu, Marios C. Papaefthymiou
HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (7) (2005)
Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers (2005)
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
Charge-Recovery Computing on Silicon. IEEE Trans. Computers 54 (6) (2005)
Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE (2005)
Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
A GHz-class charge recovery logic. ISLPED (2005)
Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI (2005)
Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler
Two-Phase Resonant Clock Distribution. ISVLSI (2005)
Jiyoun Kim, José Neves, Marios C. Papaefthymiou
Multi-Session Partitioning for Parallel Timing Optimization. PDCAT (2005)
Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
Practical repeater insertion for low power: what repeater library do we need? DAC (2004)
Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab
An Algorithm for Geometric Load Balancing with Two Constraints. IPDPS (2004)
Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
Experimental Evaluation of Resonant Clock Distribution. ISVLSI (2004)
Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
Empirical evaluation of timing and power in resonant clock distribution. ISCAS (2) (2004)
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
Clock tree layout design for reduced delay uncertainty. SoCC (2004)
Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky
A synchronous interface for SoCs with multiple clock domains. SoCC (2004)
Xun Liu, Marios C. Papaefthymiou
A Markov chain sequence generator for power macromodeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (7) (2004)
Joohee Kim, Marios C. Papaefthymiou
Constant-load energy recovery memory for efficient high-speed operation. ISLPED (2004)
Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou
Energy Recovering ASIC Design. ISVLSI (2003)
Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou
A 225 MHz resonant clocked ASIC chip. ISLPED (2003)
Xun Liu, Marios C. Papaefthymiou
Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. Very Large Scale Integr. Syst. 11 (6) (2003)
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
Fine-grain real-time reconfigurable pipelining. IBM J. Res. Dev. 47 (5-6) (2003)
Joohee Kim, Marios C. Papaefthymiou
Block-based multiperiod dynamic memory design for low data-retention power. IEEE Trans. Very Large Scale Integr. Syst. 11 (6) (2003)
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE (2003)
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
A true single-phase energy-recovery multiplier. IEEE Trans. Very Large Scale Integr. Syst. 11 (2) (2003)
Xun Liu, Marios C. Papaefthymiou
HyPE: hybrid power estimation for IP-based programmable systems. ASP-DAC (2003)
Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
Energy recovering static memory. ISLPED (2002)
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
Retiming and clock scheduling for digital circuit optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (2) (2002)
Xun Liu, Marios C. Papaefthymiou
A Markov chain sequence generator for power macromodeling. ICCAD (2002)
Xun Liu, Marios C. Papaefthymiou
Design of a high-throughput low-power IS95 Viterbi decoder. DAC (2002)
Xun Liu, Marios C. Papaefthymiou
Incorporation of input glitches into power macromodeling. ISCAS (4) (2002)
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. ARVLSI (2001)
Xun Liu, Marios C. Papaefthymiou
A static power estimation methodolodgy for IP-based design. DATE (2001)
Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou
Symbolic debugging of embedded hardware and software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (3) (2001)
Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
A True Single-Phase 8-bit Adiabatic Multiplier. DAC (2001)
Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
A resonant clock generator for single-phase adiabatic systems. ISLPED (2001)
Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) (2001)
Suhwan Kim, Marios C. Papaefthymiou
True single-phase adiabatic circuitry. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
Optimizing computations for effective block-processing. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou
Symbolic debugging of globally optimized behavioral specifications. ASP-DAC (2000)
Joohee Kim, Marios C. Papaefthymiou
Dynamic Memory Design for Low Data-Retention Power. PATMOS (2000)
Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou
Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors. Des. Autom. Embed. Syst. 4 (4) (1999)
Suhwan Kim, Marios C. Papaefthymiou
Single-phase source-coupled adiabatic logic. ISLPED (1999)
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
Maximizing Performance by Retiming and Clock Skew Scheduling. DAC (1999)
Giuseppe Bernacchia, Marios C. Papaefthymiou
Analytical macromodeling for high-level power estimation. ICCAD (1999)
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE (1999)
Marios C. Papaefthymiou
Asymptotically efficient retiming under setup and hold constraints. ICCAD (1998)
Suhwan Kim, Marios C. Papaefthymiou
True single-phase energy-recovering logic for low-power, high-speed VLSI. ISLPED (1998)
Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante
Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. JSSPP (1997)
Kumar N. Lalgudi, Marios C. Papaefthymiou
Computing Strictly-Second Shortest Paths. Inf. Process. Lett. 63 (4) (1997)
Kumar N. Lalgudi, Marios C. Papaefthymiou
Retiming edge-triggered circuits under general delay models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (12) (1997)
Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou
Optimizing two-phase, level-clocked circuitry. J. ACM 44 (1) (1997)
Marios C. Papaefthymiou, Kumar N. Lalgudi
Fixed-phase retiming for low power design. ISLPED (1996)
Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante
A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. JSSPP (1996)
Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou
An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. SPAA (1996)
Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
-Delay Problem. DAC (1996)
Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou
Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. Perform. Evaluation (4) (1996)
Kumar N. Lalgudi, Marios C. Papaefthymiou
DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. DAC (1995)
Kumar N. Lalgudi, Marios C. Papaefthymiou
Efficient retiming under a general delay model. ARVLSI (1995)
Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
Precomputation-based sequential logic optimization for low power. ICCAD (1994)
Marios C. Papaefthymiou, Joseph Rodrigue
Implementing parallel shortest-paths algorithms. Parallel Algorithms (1994)
Marios C. Papaefthymiou
Understanding Retiming Through Maximum Avarage-Delay Cycles. Math. Syst. Theory 27 (1) (1994)
Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. 2 (4) (1994)
Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou
Memory Assignment for Multiprocessor Caches through Grey Coloring. PARLE (1994)
Marios C. Papaefthymiou, Keith H. Randall
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. DAC (1993)
Marios C. Papaefthymiou
Understanding Retiming Through Maximum Average-Weight Cycles. SPAA (1991)