Taewhan Kim

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 86

Top Venues

Integr.

DATE

ICCAD

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi, Taewhan Kim
BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. DATE (2024)
Soomin Kim, Taewhan Kim
Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (5) (2024)
Jaehoon Ahn, Kyungjoon Chang, Kyumyung Choi, Taewhan Kim, Heechun Park
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Kyeonghyeon Baek, Taewhan Kim
CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. DATE (2024)
Hwapyong Kim, Taewhan Kim
Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing. ISCAS (2024)
Suwan Kim, Hyunbum Park, Kyeonghyeon Baek, Kyumyung Choi, Taewhan Kim
Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model. ISPD (2024)
Jooyeon Jeong, Taewhan Kim
Placement legalization for heterogeneous cells of non-integer multiple-heights. Integr. 97 (2024)
Taewhan Kim
Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024). IEEE Des. Test 41 (3) (2024)
Sora Park, Taewhan Kim
Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating. ISCAS (2023)
Hwapyong Kim, Taewhan Kim
Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool. ACM Great Lakes Symposium on VLSI (2023)
Taewhan Kim
Challenges on Design and Technology Co-Optimization: Design Automation Perspective. MWSCAS (2023)
Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. DATE (2023)
Doyeon Won, Soomin Kim, Taewhan Kim
Machine Learning Driven Synthesis of Clock Gating. ISLPED (2023)
Eunsol Jeong, Taewhan Kim, Heechun Park
Eliminating Minimum Implant Area Violations With Design Quality Preservation. IEEE Trans. Very Large Scale Integr. Syst. 31 (5) (2023)
Jaewan Yang, Taewhan Kim
Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling. SOCC (2023)
Ilseon Ha, Taewhan Kim
Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow. ISOCC (2023)
Suwan Kim, Taewhan Kim
Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops. ICCAD (2023)
Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim
Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. DATE (2023)
Jinmyoung Kim, Taewhan Kim
Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips. ISOCC (2023)
Chaehyun Kim, Taewhan Kim
Maximizing Power Saving Through State-Driven Clock Gating. ISOCC (2023)
Kihwan Jeon, Taewhan Kim
Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells. ISOCC (2023)
Doyeon Won, Taewhan Kim
Improving Pin Accessibility of Standard Cells Through Fin Depopulation. ISCAS (2022)
Suwan Kim, Taewhan Kim
Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model. DATE (2022)
Soomin Kim, Taewhan Kim
Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells. ICCAD (2022)
Jeongwoo Heo, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyumyung Choi
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Kyungjoon Chang, Taewhan Kim
Analysis of Impacting Multi-stack Standard Cells on Chip Implementation. ISOCC (2022)
Eunsol Jeong, Heechun Park, Taewhan Kim
A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. DATE (2022)
Heechun Park, Taewhan Kim
Speeding-up neuromorphic computation for neural networks: Structure optimization approach. Integr. 82 (2022)
Jongsung Kang, Taewhan Kim
Improving Speed of MUX-FSM-based Stochastic Computing for On-device Neural Networks. J. Comput. Sci. Eng. 16 (2) (2022)
Soomin Kim, Taewhan Kim
Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops. ISCAS (2022)
Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. ISLPED (2022)
Sora Park, Taewhan Kim
Selective Clock Gating Based on Comprehensive Power Saving Analysis. ISCAS (2022)
Sehyeon Chung, Jooyeon Jeong, Taewhan Kim
Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. ISLPED (2022)
Byungmin Ahn, Taewhan Kim
Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Hyoungjoon Lim, Soohyun Kim, Kyong-Mee Chung, Kangjae Lee, Taewhan Kim, Joon Heo
Is college students' trajectory associated with academic performance? Comput. Educ. 178 (2022)
Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. ICCAD (2022)
Jaehoon Ahn, Taewhan Kim
Neural Network Model for Detour Net Prediction. SLIP (2022)
Sehyeon Chung, Taewhan Kim
ECO routing based on network flow method. Integr. 86 (2022)
Kyeonghyeon Baek, Taewhan Kim
Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis. ICCAD (2021)
Jeongwoo Heo, Taewhan Kim
Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Kyeongrok Jo, Taewhan Kim
Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis. ICCD (2021)
Taehwan Kim, Heechun Park, Taewhan Kim
Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. IEEE Trans. Very Large Scale Integr. Syst. 29 (3) (2021)
Byungmin Ahn, Taewhan Kim
Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks. J. Circuits Syst. Comput. 30 (9) (2021)
Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim
Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. ISOCC (2021)
Suwan Kim, Kyeongrok Jo, Taewhan Kim
Boosting Pin Accessibility Through Cell Layout Topology Diversification. ASP-DAC (2021)
Changho Han, Taewhan Kim
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits. Integr. 78 (2021)
Jongsung Kang, Taewhan Kim
Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks. DATE (2021)
Suwan Kim, Taewhan Kim
Practical Approach to Cell Replacement for Resolving Pin Inaccessibility. MWSCAS (2021)
Jaejoon Yoon, Sehyeon Chung, Taewhan Kim
Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. ISOCC (2021)
Jooyeon Jeong, Taewhan Kim
Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures. MWSCAS (2021)
Soomin Kim, Taewhan Kim
Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits. ISQED (2021)
Eunsol Jeong, Heechun Park, Jooyeon Jeong, Taewhan Kim
Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. MWSCAS (2021)
Jeongwoo Heo, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. ASP-DAC (2020)
Jongsung Kang, Taewhan Kim
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks. Integr. 71 (2020)
Taewhan Kim, Kangsoo Jung, Seog Park
Sparsity Reduction Technique Using Grouping Method for Matrix Factorization in Differentially Private Recommendation Systems. IEICE Trans. Inf. Syst. (7) (2020)
Taehwan Kim, Gyoung-Hwan Hyun, Taewhan Kim
Steady state driven power gating for lightening always-on state retention storage. ISLPED (2020)
Jeongwoo Heo, Taewhan Kim
Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. ASP-DAC (2020)
Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyu-Myung Choi
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. Integr. 74 (2020)
Byungmin Ahn, Taewhan Kim
Deeper Weight Pruning without Accuracy Loss in Deep Neural Networks. DATE (2020)
Kyeongrok Jo, Seyong Ahn, Jungho Do, Taejoong Song, Taewhan Kim, Kyu-Myung Choi
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. IEEE Trans. Very Large Scale Integr. Syst. 27 (8) (2019)
Gyoung-Hwan Hyun, Taewhan Kim
Flip-flop State Driven Clock Gating: Concept, Design, and Methodology. ICCAD (2019)
Taehwan Kim, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. ISVLSI (2019)
Gyoung-Hwan Hyun, Taewhan Kim
Allocation of State Retention Registers Boosting Practical Applicability to Power Gated Circuits. ICCAD (2019)
Heechun Park, Taewhan Kim
Hybrid asynchronous circuit generation amenable to conventional EDA flow. Integr. 64 (2019)
Byungmin Ahn, Taewhan Kim
Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks. SoCC (2018)
Youngchan Kim, Taewhan Kim
Synthesis and exploration of clock spines. IET Comput. Digit. Tech. 12 (5) (2018)
Kyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyu-Myung Choi
Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. ASP-DAC (2018)
Joohan Kim, Taewhan Kim
Clock buffer and flip-flop co-optimization for reducing peak current noise. ISQED (2018)
Juyeon Kim, Taewhan Kim
Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network. ISQED (2018)
Heechun Park, Taewhan Kim
Structure optimizations of neuromorphic computing architectures for deep neural network. DATE (2018)
Giyoung Yang, Taewhan Kim
Design and algorithm for clock gating and flip-flop co-optimization. ICCAD (2018)
Hyoungseok Moon, Taewhan Kim
Loosely coupled multi-bit flip-flop allocation for power reduction. Integr. 58 (2017)
Youngchan Kim, Taewhan Kim
Algorithm for synthesis and exploration of clock spines. ASP-DAC (2017)
Joohan Kim, Taewhan Kim
Boundary optimization of buffered clock trees for low power. Integr. 56 (2017)
Juyeon Kim, Taewhan Kim
Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (4) (2017)
Dongyoun Yi, Taewhan Kim
Switch cell optimization of power-gated modern system-on-chips. ICCAD (2017)
Deokjin Joo, Taewhan Kim
Clock buffer polarity assignment under useful skew constraints. Integr. 57 (2017)
Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (12) (2016)
Juyeon Kim, Deokjin Joo, Taewhan Kim
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. Integr. 52 (2016)
Jeongwoo Heo, Taewhan Kim
Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model. ISVLSI (2016)
Heechun Park, Taewhan Kim
Synthesizing Asynchronous Circuits toward Practical Use. ISVLSI (2016)
Dongyoun Yi, Taewhan Kim
Allocation of multi-bit flip-flops in logic synthesis for power optimization. ICCAD (2016)
Hyoungjun Jeon, Taewhan Kim
Grey-level context-driven histogram equalisation. IET Image Process. 10 (5) (2016)
Hyoungseok Moon, Taewhan Kim
Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization. ASP-DAC (2016)
Deokjin Joo, Taewhan Kim
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. ASP-DAC (2016)
Lu Cai, Taewhan Kim
Context-driven hybrid image inpainting. IET Image Process. 9 (10) (2015)
Heechun Park, Taewhan Kim
Synthesis of TSV Fault-Tolerant 3-D Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2) (2015)
Hyungjung Seo, Juyeon Kim, Minseok Kang, Taewhan Kim
Synthesis for Power-Aware Clock Spines. ICCAD (2015)
Hyungjung Seo, Jeongwoo Heo, Taewhan Kim
Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing. ISQED (2015)
Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. ASP-DAC (2015)
Juyeon Kim, Taewhan Kim
Useful clock skew scheduling using adjustable delay buffers in multi-power mode designs. ASP-DAC (2015)
Kitae Park, Geunho Kim, Taewhan Kim
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs. DATE (2014)
Sangdo Park, Taewhan Kim
Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs. MWSCAS (2014)
Minseok Kang, Taewhan Kim
Integrated Resource Allocation and Binding in Clock Mesh Synthesis. ACM Trans. Design Autom. Electr. Syst. 19 (3) (2014)
Deokjin Joo, Taewhan Kim
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (3) (2014)
Byunghyun Lee, Taewhan Kim
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs. Integr. 47 (2) (2014)
Myung Woo Lee, Taewhan Kim
Fast algorithm of low power image reformation for OLED display. ICDIP (2014)
Hyungjung Seo, Taewhan Kim
Post-silicon tunable clock buffer allocation based on fast chip yield computation. ISQED (2014)
Sangdo Park, Taewhan Kim
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis. Integr. 47 (4) (2014)

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Publication Activity (10 Years)

Top Topics

Top Venues

Taewhan Kim