Heechun Park

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 26

Top Topics

Physical Design

Reachability Analysis

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Suwan Kim, Heechun Park
Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (7) (2024)
Jaehoon Ahn, Kyungjoon Chang, Kyumyung Choi, Taewhan Kim, Heechun Park
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Junghyun Yoon, Heechun Park
Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations. ISQED (2024)
Dho Ui Lim, Heechun Park
Graph Neural Network-Based Detailed Placement Optimization Framework. ISQED (2024)
Sojung Park, Heechun Park
Timing-Aware Tier Partitioning for 3D ICs with Critical Path Consideration. ICEIC (2024)
Kyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. DATE (2023)
Eunsol Jeong, Taewhan Kim, Heechun Park
Eliminating Minimum Implant Area Violations With Design Quality Preservation. IEEE Trans. Very Large Scale Integr. Syst. 31 (5) (2023)
Eunsol Jeong, Heechun Park, Taewhan Kim
A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. DATE (2022)
Heechun Park, Taewhan Kim
Speeding-up neuromorphic computation for neural networks: Structure optimization approach. Integr. 82 (2022)
Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. ISLPED (2022)
Arjun Chaudhuri, Sanmitra Banerjee, Jinwoo Kim, Heechun Park, Bon Woong Ku, Sukeshwar Kannan, Krishnendu Chakrabarty, Sung Kyu Lim
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs. ACM J. Emerg. Technol. Comput. Syst. 18 (1) (2022)
Taehwan Kim, Heechun Park, Taewhan Kim
Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. IEEE Trans. Very Large Scale Integr. Syst. 29 (3) (2021)
Heechun Park, Kyungjoon Chang, Jooyeon Jeong, Jaehoon Ahn, Ki-Seok Chung, Taewhan Kim
Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. ISOCC (2021)
Seyoung Kim, Heechun Park, Jaeha Kim
Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis. ISOCC (2021)
Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements. ACM Trans. Design Autom. Electr. Syst. 26 (5) (2021)
Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna, Sung Kyu Lim
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems. IEEE Trans. Very Large Scale Integr. Syst. 29 (4) (2021)
Eunsol Jeong, Heechun Park, Jooyeon Jeong, Taewhan Kim
Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. MWSCAS (2021)
Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Jinwoo Kim, Gauthaman Murali, Edward Lee, Daehyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay, Krishnendu Chakrabarty
Advances in Design and Test of Monolithic 3-D ICs. IEEE Des. Test 37 (4) (2020)
Heechun Park, Bon Woong Ku, Kyungwook Chang, Da Eun Shim, Sung Kyu Lim
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs. ISPD (2020)
Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Heechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim
RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs. DAC (2019)
Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse. DAC (2019)
Arjun Chaudhuri, Sanmitra Banerjee, Heechun Park, Bon Woong Ku, Krishnendu Chakrabarty, Sung Kyu Lim
Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs. ETS (2019)
Heechun Park, Taewhan Kim
Hybrid asynchronous circuit generation amenable to conventional EDA flow. Integr. 64 (2019)
Heechun Park, Taewhan Kim
Structure optimizations of neuromorphic computing architectures for deep neural network. DATE (2018)
Heechun Park, Taewhan Kim
Synthesizing Asynchronous Circuits toward Practical Use. ISVLSI (2016)
Heechun Park, Taewhan Kim
Synthesis of TSV Fault-Tolerant 3-D Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (2) (2015)
Heechun Park, Taewhan Kim
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. ICCAD (2013)