Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse.
Jinwoo KimGauthaman MuraliHeechun ParkEric QinHyoukjun KwonVenkata Chaitanya Krishna ChekuriNael Mizanur RahmanNihar DasariArvind SinghMinah LeeHakki Mert TorunKallol RoyMadhavan SwaminathanSaibal MukhopadhyayTushar KrishnaSung Kyu LimPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2020)
Keyphrases
- hardware software
- loosely coupled
- vlsi implementation
- low cost
- analog vlsi
- host computer
- high speed
- heterogeneous systems
- heterogeneous environments
- level parallelism
- reconfigurable hardware
- data integration
- seamless integration
- real time
- heterogeneous databases
- modular design
- learning objects
- software architecture
- object oriented