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Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs.

Arjun ChaudhuriSanmitra BanerjeeHeechun ParkBon Woong KuKrishnendu ChakrabartySung Kyu Lim
Published in: ETS (2019)
Keyphrases
  • inter layer
  • built in self test
  • integrated circuit
  • single layer
  • scalable video coding
  • base layer
  • inter frame
  • rate distortion
  • bitstream
  • bi level
  • artificial neural networks
  • coding efficiency