Deokjin Joo

Publication Activity (10 Years)

Years Active: 2011-2017
Publications (10 Years): 4

Top Topics

Optimal Allocation

Performs Poorly

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Keunwoo Choi, Deokjin Joo, Juho Kim
Kapre: On-GPU Audio Preprocessing Layers for a Quick Implementation of Deep Neural Network Models with Keras. CoRR (2017)
Deokjin Joo, Taewhan Kim
Clock buffer polarity assignment under useful skew constraints. Integr. 57 (2017)
Juyeon Kim, Deokjin Joo, Taewhan Kim
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. Integr. 52 (2016)
Deokjin Joo, Taewhan Kim
Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. ASP-DAC (2016)
Deokjin Joo, Taewhan Kim
A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (3) (2014)
Kyoung-Hwan Lim, Deokjin Joo, Taewhan Kim
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Juyeon Kim, Deokjin Joo, Taewhan Kim
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. DAC (2013)
Deokjin Joo, Minseok Kang, Taewhan Kim
Design Methodologies for Reliable Clock Networks. J. Comput. Sci. Eng. 6 (4) (2012)
YongHwan Kim, Minseok Kang, Kyoung-Hwan Lim, Sangdo Park, Deokjin Joo, Taewhan Kim
Clock design techniques considering circuit reliability. ISOCC (2011)
Hochang Jang, Deokjin Joo, Taewhan Kim
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (1) (2011)
Deokjin Joo, Taewhan Kim
WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. DAC (2011)