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Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling.
Seyong Ahn
Minseok Kang
Marios C. Papaefthymiou
Taewhan Kim
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2016)
Keyphrases
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