Boundary optimization of buffered clock trees for low power.
Joohan KimTaewhan KimPublished in: Integr. (2017)
Keyphrases
- low power
- power consumption
- high speed
- low cost
- single chip
- high power
- digital signal processing
- wireless transmission
- vlsi circuits
- low power consumption
- vlsi architecture
- cmos technology
- gate array
- mixed signal
- power reduction
- logic circuits
- power saving
- power dissipation
- image sensor
- delay insensitive
- real time
- signal processing
- video sequences
- image processing