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Clock tree layout design for reduced delay uncertainty.

Dimitrios VelenisMarios C. PapaefthymiouEby G. Friedman
Published in: SoCC (2004)
Keyphrases
  • layout design
  • integer programming
  • tree structure
  • high speed
  • neural network
  • power consumption
  • uncertain data
  • tunnel boring machine
  • special case
  • virtual reality
  • multicast tree