Juang-Ying Chueh

Publication Activity (10 Years)

Years Active: 2004-2021
Publications (10 Years): 1

Top Topics

Computationally Expensive

Image Processing

Multiresolution

Top Venues

Publications

Nicky Lu, Chun Shiah, Juang-Ying Chueh, Bor-Doou Rong, Wei-Jr Huang, Ho-Yin Chen, Cheng-Nan Chang, Chia-Wei Chang, Tzung-Shen Chen
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns. VLSI Circuits (2021)
Juang-Ying Chueh, Chuck Tung
Efficient standard cell abutment checker. ICECS (2013)
Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou
Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits 42 (1) (2007)
Visvesh S. Sathe, Juang-Ying Chueh, Marios Papaefthymio
A 1.1ghz charge-recovery logic. ISSCC (2006)
Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC (2006)
Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers (2005)
Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler
Two-Phase Resonant Clock Distribution. ISVLSI (2005)
Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
Experimental Evaluation of Resonant Clock Distribution. ISVLSI (2004)
Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
Empirical evaluation of timing and power in resonant clock distribution. ISCAS (2) (2004)