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Nicky Lu
Publication Activity (10 Years)
Years Active: 2007-2021
Publications (10 Years): 4
Top Topics
Information Integration
Heterogeneous Databases
High Density
Ai Technologies
Top Venues
VLSI Circuits
VLSIC
DRC
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Publications
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Nicky Lu
Optimizing Monolithic and Heterogeneous Integration to Create Intelligent-Grand-Scale-Integration for Smart MicroSystems.
DRC
(2021)
Nicky Lu
,
Chun Shiah
,
Juang-Ying Chueh
,
Bor-Doou Rong
,
Wei-Jr Huang
,
Ho-Yin Chen
,
Cheng-Nan Chang
,
Chia-Wei Chang
,
Tzung-Shen Chen
Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.
VLSI Circuits
(2021)
Chun Shiah
,
C. N. Chang
,
Richard Crisp
,
C. P. Lin
,
C. N. Pan
,
C. P. Chuang
,
H. L. Chen
,
S. H. Jheng
,
T. F. Chang
,
W. J. Huang
,
K. C. Ting
,
Rick Dai
,
W. M. Huang
,
Bor-Doou Rong
,
Nicky Lu
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems.
VLSI Circuits
(2019)
Pei-Wen Luo
,
Chi-Kang Chen
,
Yu-Hui Sung
,
Wei Wu
,
Hsiu-Chuan Shih
,
Chia-Hsin Lee
,
Kuo-Hua Lee
,
Ming-Wei Li
,
Mei-Chiang Lung
,
Chun-Nan Lu
,
Yung-Fa Chou
,
Po-Lin Shih
,
Chung-Hu Ke
,
Chun Shiah
,
Patrick Stolt
,
Shigeki Tomishima
,
Ding-Ming Kwai
,
Bor-Doou Rong
,
Nicky Lu
,
Shih-Lien Lu
,
Cheng-Wen Wu
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
VLSIC
(2015)
Nicky Lu
,
Leland Chang
,
Daisaburo Takashima
Future system and memory architectures: Transformations by technology and applications.
ISSCC
(2011)
Sreedhar Natarajan
,
Nicky Lu
Private Equity: Fight them or Invite them.
ISSCC
(2008)
Nicky Lu
,
Shyh-Jye Jou
Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07).
IEEE J. Solid State Circuits
43 (11) (2008)
Nicky Lu
,
C. K. Wang
,
Philip Wong
,
Sreedhar Natarajan
E1 Ultimate Limits of Integrated Electronics.
ISSCC
(2007)