Wei Wu

Publication Activity (10 Years)

Years Active: 2004-2017
Publications (10 Years): 2

Top Topics

Lower Error Rates

Authentication Scheme

Memory Hierarchy

Top Venues

Publications

Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC (2017)
Pei-Wen Luo, Chi-Kang Chen, Yu-Hui Sung, Wei Wu, Hsiu-Chuan Shih, Chia-Hsin Lee, Kuo-Hua Lee, Ming-Wei Li, Mei-Chiang Lung, Chun-Nan Lu, Yung-Fa Chou, Po-Lin Shih, Chung-Hu Ke, Chun Shiah, Patrick Stolt, Shigeki Tomishima, Ding-Ming Kwai, Bor-Doou Rong, Nicky Lu, Shih-Lien Lu, Cheng-Wen Wu
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. VLSIC (2015)
Patrick Koeberl, Jiangtao Li, Anand Rajan, Wei Wu
Entropy loss in PUF-based key generation schemes: The repetition code pitfall. HOST (2014)
Patrick Koeberl, Jiangtao Li, Wei Wu
A Spatial Majority Voting Technique to Reduce Error Rate of Physically Unclonable Functions. INTRUST (2013)
Patrick Koeberl, Jiangtao Li, Roel Maes, Anand Rajan, Claire Vishik, Marcin Wójcik, Wei Wu
A practical device authentication scheme using SRAM PUFs. J. Cryptogr. Eng. 2 (4) (2012)
Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
Direct Compare of Information Coded With Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu
Adaptive Cache Design to Enable Reliable Low-Voltage Operation. IEEE Trans. Computers 60 (1) (2011)
Patrick Koeberl, Jiangtao Li, Anand Rajan, Claire Vishik, Wei Wu
A Practical Device Authentication Scheme Using SRAM PUFs. TRUST (2011)
Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu
Energy-efficient cache design using variable-strength error-correcting codes. ISCA (2011)
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu
Reducing cache power with low-cost, multi-bit error-correcting codes. ISCA (2010)
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu
Improving cache lifetime reliability at ultra-low voltages. MICRO (2009)
Pu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala
FEKIS: a fast architecture-level thermal analyzer for online thermal regulation. ACM Great Lakes Symposium on VLSI (2008)
Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, Murli Tirumala
A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation. J. Low Power Electron. 4 (2) (2008)
Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
Efficient power modeling and software thermal sensing for runtime temperature monitoring. ACM Trans. Design Autom. Electr. Syst. 12 (3) (2007)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-Based Design Exploration of DVS in Network Processor Architectures CoRR (2007)
Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu
Improving the reliability of on-chip data caches under process variations. ICCD (2007)
Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang
Reduce Register Files Leakage Through Discharging Cells. ICCD (2006)
Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
A systematic method for functional unit power estimation in microprocessors. DAC (2006)
Pu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
Fast Thermal Simulation for Runtime Temperature Tracking and Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. ICCD (2005)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE (2005)
Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
Fast thermal simulation for architecture level dynamic thermal management. ICCAD (2005)
Lingling Jin, Wei Wu, Jun Yang, Chuanjun Zhang, Youtao Zhang
Dynamic Co-allocation of Level One Caches. ICESS (2005)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-based power/performance analysis of network processor architectures. HLDVT (2004)