Xi Chen

Publication Activity (10 Years)

Years Active: 2002-2011
Publications (10 Years): 0

Publications

Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. DAC (2011)
Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. 13 (4) (2009)
Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh
Bridging RTL and gate: correlating different levels of abstraction for design debugging. HLDVT (2007)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-Based Design Exploration of DVS in Network Processor Architectures CoRR (2007)
Xi Chen, Harry Hsieh, Felice Balarin
Verification Approach of Metropolis Design Framework for Embedded Systems. Int. J. Parallel Program. 34 (1) (2006)
Eric Cheung, Piyush Satapathy, Vi Pham, Harry Hsieh, Xi Chen
Runtime Deadlock Analysis of SystemC Designs. HLDVT (2006)
Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli
Communication and co-simulation infrastructure for heterogeneous system integration. DATE (2006)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE (2005)
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
Simulation based deadlock analysis for system level designs. DAC (2005)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (8) (2004)
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
Utilizing Formal Assertions for System Design of Network Processors. DATE (2004)
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
Assertion Based Verification and Analysis of Network Processor Architectures. Des. Autom. Embed. Syst. 9 (3) (2004)
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
Assertion-based power/performance analysis of network processor architectures. HLDVT (2004)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Verifying LOC based functional and performance constraints. HLDVT (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. 8 (2-3) (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Automatic trace analysis for logic of constraints. DAC (2003)
Yan Luo, Laxmi Narayan Bhuyan, Xi Chen
Shared memory multiprocessor architectures for software IP routers. IEEE Trans. Parallel Distributed Syst. 14 (12) (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Case Studies of Model Checking for Embedded System Designs. ACSD (2003)
Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Formal verification of embedded system designs at multiple levels of abstraction. HLDVT (2002)