Yu-Chin Hsu

Publication Activity (10 Years)

Years Active: 1988-2020
Publications (10 Years): 3

Top Topics

Intelligent Multimedia

Theory Of Planned Behavior

Software Development Projects

Senior Citizens

Top Venues

J. Ambient Intell. Humaniz. Comput.

Publications

Yu-Chin Hsu, Robert Chen-Hao Chang
Intelligent Chips and Technologies for AIoT Era. A-SSCC (2020)
Ming-Yuan Hsieh, Yu-Chin Hsu, Ching-Torng Lin
Risk assessment in new software development projects at the front end: a fuzzy logic approach. J. Ambient Intell. Humaniz. Comput. 9 (2) (2018)
Chia-Chien Hsu, Yu-Chin Hsu, Ching-Torng Lin
Towards Understanding Senior Citizens' Gateball Participations Behavior and Well-Being: An Application of the Theory of Planned Behavior. HCI (5) (2016)
Yu-Chin Hsu, Rong-Huei Chen, Chih-Ming Fan
Identifying ill tool combinations via Gibbs sampler for semiconductor manufacturing yield diagnosis. WSC (2012)
Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. DAC (2011)
Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu
A General Failure Candidate Ranking Framework for Silicon Debug. VTS (2008)
Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh
Bridging RTL and gate: correlating different levels of abstraction for design debugging. HLDVT (2007)
Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang
Visibility enhancement for silicon debug. DAC (2006)
Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu
Diagnosing Silicon Failures Based on Functional Test Patterns. MTV (2006)
Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai
Advanced techniques for RTL debugging. DAC (2003)
Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. ACM Trans. Design Autom. Electr. Syst. 7 (1) (2002)
Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
Timing optimization on routed designs with incremental placementand routing characterization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (2) (2000)
Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
Post-routing timing optimization with routing characterization. ISPD (1999)
Enoch Hwang, Frank Vahid, Yu-Chin Hsu
FSMD Functional Partitioning for Low Power. DATE (1999)
Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. ACM Trans. Design Autom. Electr. Syst. 3 (2) (1998)
Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee
Eliminating false loops caused by sharing in control path. ACM Trans. Design Autom. Electr. Syst. 3 (3) (1998)
Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee
On the control-subroutine implementation of subprogram synthesis. ASP-DAC (1997)
Fur-Shing Tsai, Yu-Chin Hsu
Layout Modeling and Design Space Exploration in Pss1 System. VLSI Design 5 (2) (1997)
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. Des. Autom. Embed. Syst. 2 (3-4) (1997)
Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
A Comparison of Functional and Structural Partitioning. ISSS (1996)
Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee
Eliminating False Loops Caused by Sharing in Control Path. ISSS (1996)
How-Rern Lin, Yu-Chin Hsu, TingTing Hwang
Cell height driven transistor sizing in a cell based static CMOS module design. IEEE J. Solid State Circuits 31 (5) (1996)
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC (1996)
Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. Microprocess. Microprogramming 41 (7) (1995)
Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang
Synthesis of false loop free circuits. ASP-DAC (1995)
Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
A new approach to schedule operations across nested-ifs and nested-loops. Microprocess. Microprogramming 41 (1) (1995)
How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC (1994)
Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures. IEEE Trans. Very Large Scale Integr. Syst. 2 (1) (1994)
Ting-Hai Chao, Yu-Chin Hsu
Rectilinear Steiner tree construction by local and global refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (3) (1994)
Cheng-Tsung Hwang, Yu-Chin Hsu
Zone scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (7) (1993)
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (3) (1993)
Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee
High throughput pipelined data path synthesis by conserving the regularity of nested loops. ICCAD (1993)
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
PLS: a scheduler for pipeline synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (9) (1993)
Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang
A new approach to schedule operations across nested-ifs and nested-loops. MICRO (1992)
Fur-Shing Tsai, Yu-Chin Hsu
STAR: An automatic data path allocator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (9) (1992)
Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho
Zero Skew Clock Net Routing. DAC (1992)
Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu
Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. ICCAD (1991)
Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
LiB: a CMOS cell compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (8) (1991)
Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao
Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40 (6) (1991)
Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu
A formal approach to the scheduling problem in high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (4) (1991)
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC (1991)
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
Scheduling for Functional Pipelining and Loop Winding. DAC (1991)
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
Hybrid routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (2) (1990)
Ting-Hai Chao, Yu-Chin Hsu
Rectilinear Steiner Tree Construction by Local and Global Refinement. ICCAD (1990)
Fur-Shing Tsai, Yu-Chin Hsu
Data Path Construction and Refinement. ICCAD (1990)
Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin
Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC (1990)
Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu
Data Path Allocation Based on Bipartite Weighted Matching. DAC (1990)
Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (7) (1990)
Youn-Long Lin, Yu-Chin Hsu
A new algorithm for tile generation. Integr. 9 (3) (1990)
Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
LiB: A Cell Layout Generator. DAC (1990)
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
SILK: a simulated evolution router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (10) (1989)
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
Routing using a pyramid data structure. ICCAD (1989)
Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
An optimal transistor-chaining algorithm for CMOS cell layout. ICCAD (1989)
Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin
A new integer linear programming formulation for the scheduling problem in data path synthesis. ICCAD (1989)
Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
A detailed router based on simulated evolution. ICCAD (1988)