EDAC-ETC-EUROASIC

Keyphrases

Publications

1994

Yih-Lang Li, Cheng-Wen Wu
Logic and Fault Simulation by Cellular Automata. EDAC-ETC-EUROASIC (1994)
Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC (1994)
M. Straube, Wolfgang Wilkes, Gunter Schlageter
HANDICAP - A System for Design Consulting. EDAC-ETC-EUROASIC (1994)
Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. EDAC-ETC-EUROASIC (1994)
Shan-Hsi Huang, Jan M. Rabaey
Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations. EDAC-ETC-EUROASIC (1994)
Daniel Gajski, Frank Vahid, Sanjiv Narayan
A System-Design Methodology: Executable-Specification Refinement. EDAC-ETC-EUROASIC (1994)
Peter Zepter, Thorsten Grötker
Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations. EDAC-ETC-EUROASIC (1994)
Sandip Parikh, Michael L. Bushnell, James Sienicki, Ganesh Ramakrishnan
Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework. EDAC-ETC-EUROASIC (1994)
Matti Kärkkäinen, Kari Tiensyrjä, Matti Weissenfelt
Boundary Scan Testing Combined with Power Supply Current Monitoring. EDAC-ETC-EUROASIC (1994)
Peter T. Breuer, Luis Sánchez Fernández, Carlos Delgado Kloos
Clean formal semantics for VHDL. EDAC-ETC-EUROASIC (1994)
Koen Schoofs, Gert Goossens, Hugo De Man
Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures. EDAC-ETC-EUROASIC (1994)
Martyn Edwards, John Forrest
A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems. EDAC-ETC-EUROASIC (1994)
C. Safinia, Régis Leveugle, Gabriele Saucier
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC (1994)
How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang
Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC (1994)
Hannes C. Wittmann, Manfred Henftling
Efficient Path Identification for Delay Testing - Time and Space Optimization. EDAC-ETC-EUROASIC (1994)
Huy Nam Nguyen, J. P. Tual, L. Ducousso, Michel Thill, P. Vallet
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System. EDAC-ETC-EUROASIC (1994)
Manoj Sachdev
Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. EDAC-ETC-EUROASIC (1994)
Mani B. Srivastava, Miodrag Potkonjak
Transforming Linear Systems for Joint Latency and Throughout Optimization. EDAC-ETC-EUROASIC (1994)
Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess
On Design Rule Correct Maze Routing. EDAC-ETC-EUROASIC (1994)
Luc Burgun, N. Dictus, Alain Greiner, E. Pradho, C. Sarwary
Multilevel Logic Synthesis of Very High Complexity Circuits. EDAC-ETC-EUROASIC (1994)
Pierre Coulomb, François Pogodalla
PLFP256 A Pipelined Fourier Processor. EDAC-ETC-EUROASIC (1994)
D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC (1994)
Vincent Moser, Pascal Nussbaum, Hans Peter Amann, Luc Astier, Fausto Pellandini
A Graphical Approach to Analogue Behavioural Modelling. EDAC-ETC-EUROASIC (1994)
Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin, Hugo De Man
A Generalized Signal Transition Graph Model for Specification of Complex Interfaces. EDAC-ETC-EUROASIC (1994)
Ben Chen, Michihiro Yamazaki, Masahiro Fujita
Bug Identification of a Real Chip Design by Symbolic Model Checking. EDAC-ETC-EUROASIC (1994)
Bernd Wurth, Norbert Wehn
Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization. EDAC-ETC-EUROASIC (1994)
K. C. Koudakou
Software Implementation and Statistical Optimization of Some Electronic Component's Lifetime. EDAC-ETC-EUROASIC (1994)
Jürgen Frößl, Thomas Kropf
A New Model to Uniformly Represent the Function and Timing of MOS Circuits and its Application to VHDL Simulation. EDAC-ETC-EUROASIC (1994)
Franco Fummi, Donatella Sciuto, Micaela Serra
A Functional Approach to Delay Faults Test Generation for Sequential Circuits. EDAC-ETC-EUROASIC (1994)
Elizabeth M. Rudnick, John G. Holm, Daniel G. Saab, Janak H. Patel
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation. EDAC-ETC-EUROASIC (1994)
Oliver F. Haberl, Thomas Kropf
Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface. EDAC-ETC-EUROASIC (1994)
T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC (1994)
Chauchin Su
Random Testing of Interconnects in A Boundary Scan Environment. EDAC-ETC-EUROASIC (1994)
Yosinori Watanabe, Robert K. Brayton
State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC (1994)
Thomas Johansson, L. R. Virtanen, J. M. Gobbi
"Underground Capacitors" Very Efficient Decoupling for High Performance UHF Signal Processing ICs. EDAC-ETC-EUROASIC (1994)
Abdessatar Abderrahman, Bozena Kaminska, Yvon Savaria
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. EDAC-ETC-EUROASIC (1994)
Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC (1994)
Kimon W. Michaels, Andrzej J. Strojwas
Variable Accuracy Device Modeling for Event-Driven Circuit Simulation. EDAC-ETC-EUROASIC (1994)
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Catherine Bayol, Bernard Soulas
System-Level Modeling and Verification: a Comprehensive Design Methodology. EDAC-ETC-EUROASIC (1994)
Sen-Pin Lin, Sandeep K. Gupta, Melvin A. Breuer
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. EDAC-ETC-EUROASIC (1994)
Mokhtar Hirech, Olivier Florent, Alain Greiner, El Housseine Rejouan
A Redefinable Symbolic Simulation Technique to Testability Design Rules Checking. EDAC-ETC-EUROASIC (1994)
Sybille Hellebrand, Hans-Joachim Wunderlich
Synthesis of Self-Testable Controllers. EDAC-ETC-EUROASIC (1994)
Tarek Ben Ismail, Kevin O'Brien, Ahmed Amine Jerraya
Interactive System-level Partitioning with PARTIF. EDAC-ETC-EUROASIC (1994)
Alain Greiner, Luis Lucas, Franck Wajsbürt, Laurent Winckel
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library. EDAC-ETC-EUROASIC (1994)
Sandeep Bhatia, Niraj K. Jha
Genesis: A Behavioral Synthesis System for Hierarchical Testability. EDAC-ETC-EUROASIC (1994)
Alessandro Balboni, Claudio Costi, Franco Fummi, Donatella Sciuto
From Behavioral Description to Systolic Array Based Architectures. EDAC-ETC-EUROASIC (1994)
R. van Dongen, V. Rikkink
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array. EDAC-ETC-EUROASIC (1994)
Michael Nicolaidis, Hakim Bederr
Efficient Implementations of Self-Checking Multiply and Divide Arrays. EDAC-ETC-EUROASIC (1994)
Silvano Gai, Pier Luca Montessoro, Matteo Sonza Reorda
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits. EDAC-ETC-EUROASIC (1994)
Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò
Modeling of Broken Connections Faults in CMOS ICs. EDAC-ETC-EUROASIC (1994)