Mike Tien-Chien Lee

Publication Activity (10 Years)

Years Active: 1995-1998
Publications (10 Years): 0

Publications

Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
Cost-free scan: a low-overhead scan path design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (9) (1998)
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
Test-point insertion: scan paths through functional logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (9) (1998)
Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee
ATM switch design by high-level modeling, formal verification and high-level synthesis. ACM Trans. Design Autom. Electr. Syst. 3 (4) (1998)
Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee
Functional Scan Chain Testing. DATE (1998)
Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee
Eliminating false loops caused by sharing in control path. ACM Trans. Design Autom. Electr. Syst. 3 (3) (1998)
Vivek Tiwari, Mike Tien-Chien Lee
Power Analysis of a 32-bit Embedded Microcontroller. VLSI Design 1998 (3) (1998)
Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee
On the control-subroutine implementation of subprogram synthesis. ASP-DAC (1997)
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. Des. Autom. Embed. Syst. 2 (3-4) (1997)
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
Power analysis and minimization techniques for embedded DSP software. IEEE Trans. Very Large Scale Integr. Syst. 5 (1) (1997)
Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng
A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC (1997)
Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. DAC (1996)
Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
Instruction level power analysis and optimization of software. J. VLSI Signal Process. 13 (2-3) (1996)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
A novel methodology for transistor-level power estimation. ISLPED (1996)
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee
Sequential Permissible Functions and their Application to Circuit Optimization. ED&TC (1996)
Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee
Eliminating False Loops Caused by Sharing in Control Path. ISSS (1996)
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
Test Point Insertion: Scan Paths through Combinational Logic. DAC (1996)
Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
Instruction Level Power Analysis and Optimization of Software. VLSI Design (1996)
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC (1996)
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
Power analysis and low-power scheduling techniques for embedded DSP software. ISSS (1995)
Vivek Tiwari, Mike Tien-Chien Lee
Power analysis of a 32-bit embedded microcontroller. ASP-DAC (1995)
Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
Cost-free scan: a low-overhead scan path design methodology. ICCAD (1995)