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ATM switch design by high-level modeling, formal verification and high-level synthesis.
Sreeranga P. Rajan
Masahiro Fujita
K. Yuan
Mike Tien-Chien Lee
Published in:
ACM Trans. Design Autom. Electr. Syst. (1998)
Keyphrases
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formal verification
high level synthesis
functional verification
high level
model checking
low level
design space exploration
modeling language
model checker
case study
temporal logic
design space
parallel architecture
bounded model checking