Kuang-Chien Chen

Publication Activity (10 Years)

Years Active: 1988-2005
Publications (10 Years): 0

Publications

Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
An Efficient Sequential SAT Solver With Improved Search Strategies. DATE (2005)
Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. IEEE Des. Test Comput. 21 (2) (2004)
Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS (2002)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
Verifying sequential equivalence using ATPG techniques. ACM Trans. Design Autom. Electr. Syst. 6 (2) (2001)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49 (5) (2000)
Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska
Logic synthesis for engineering change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (3) (1999)
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
AutoFix: a hybrid tool for automatic logic rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
Cost-free scan: a low-overhead scan path design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (9) (1998)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu
Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. DAC (1998)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
AQUILA: An equivalence verifier for large sequential circuits. ASP-DAC (1997)
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
Incremental logic rectification. VTS (1997)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. ITC (1997)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
On Verifying the Correctness of Retimed Circuits. Great Lakes Symposium on VLSI (1996)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
A novel methodology for transistor-level power estimation. ISLPED (1996)
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee
Sequential Permissible Functions and their Application to Circuit Optimization. ED&TC (1996)
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
Error Correction Based on Verification Techniques. DAC (1996)
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee
Compact Vector Generation for Accurate Power Simulation. DAC (1996)
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser
An ATPG-Based Framework for Verifying Sequential Equivalence. ITC (1996)
Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
Logic rectification and synthesis for engineering change. ASP-DAC (1995)
Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
Logic Synthesis for Engineering Change. DAC (1995)
Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
Cost-free scan: a low-overhead scan path design methodology. ICCAD (1995)
Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
LUT-based FPGA technology mapping under arbitrary net-delay models. Comput. Graph. 18 (4) (1994)
Tong Gao, Chung Laung (Dave) Liu, Kuang-Chien Chen
A performance driven hierarchical partitioning placement algorithm. EURO-DAC (1993)
Kuang-Chien Chen
Boolean matching based on Boolean unification. EURO-DAC (1993)
Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. 9 (3) (1992)
Kuang-Chien Chen, Masahiro Fujita
Efficient Sum-to-One Subsets Algorithm for Logic Optimization. DAC (1992)
Kuang-Chien Chen, Jason Cong
Maximal reduction of lookup-table based FPGAs. EURO-DAC (1992)
Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD (1992)
Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen
Application of Boolean Unification to Combinational Logic Synthesis. ICCAD (1991)
Kuang-Chien Chen, Masahiro Fujita
Concurrent Resynthesis for Network Optimization. ICCD (1991)
Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
A Resynthesis Approach for Network Optimization. DAC (1991)
Kuang-Chien Chen, Saburo Muroga
Timing Optimization for Multi-Level Combinational Networks. DAC (1990)
Kuang-Chien Chen, Saburo Muroga
SYLON-DREAM: a multi-level network synthesizer. ICCAD (1989)
Kuang-Chien Chen, Saburo Muroga
Input assignment algorithm for decoded-PLAs with multi-input decoders. ICCAD (1988)