Saburo Muroga

Publication Activity (10 Years)

Years Active: 1957-1996
Publications (10 Years): 0

Publications

Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
Design of logic circuits with wired-logic utilizing transduction method. Systems and Computers in Japan 27 (11) (1996)
Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
Optimization methods for look-up table-type FPGAs based on permissible functions. Systems and Computers in Japan 27 (12) (1996)
Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga
Optimization methods for lookup-table-based FPGAs using transduction method. ASP-DAC (1995)
Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga
A Shared Memory Parallel Algorithm for Logic Synthesis. VLSI Design (1993)
Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
A Resynthesis Approach for Network Optimization. DAC (1991)
Saburo Muroga
Computer-Aided Logic Synthesis for VLSI Chips. Adv. Comput. 32 (1991)
Sung Je Hong, Saburo Muroga
Absolute Minimization of Completely Specified Switching Functions. IEEE Trans. Computers 40 (1) (1991)
Johnson Chan Limqueco, Saburo Muroga
Logic Optimization of MOS Networks. DAC (1991)
Kuang-Chien Chen, Saburo Muroga
Timing Optimization for Multi-Level Combinational Networks. DAC (1990)
Johnson Chan Limqueco, Saburo Muroga
SYLON-REDUCE: an MOS network optimization algorithms using permissible functions. ICCD (1990)
Kuang-Chien Chen, Saburo Muroga
SYLON-DREAM: a multi-level network synthesizer. ICCAD (1989)
Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney
The Transduction Method-Design of Logic Networks Based on Permissible Functions. IEEE Trans. Computers 38 (10) (1989)
Kuang-Chien Chen, Saburo Muroga
Input assignment algorithm for decoded-PLAs with multi-input decoders. ICCAD (1988)
Hung Chi Lai, Saburo Muroga
Design of MOS networks in single-rail input logic for incompletely specified functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (3) (1988)
Hung Chi Lai, Saburo Muroga
Variables. IEEE Trans. Computers 36 (2) (1987)
Robert Brian Cutler, Saburo Muroga
Derivation of Minimal Sums for Completely Specified Functions. IEEE Trans. Computers 36 (3) (1987)
Yahiko Kambayashi, Saburo Muroga
Properties of Wired Logic. IEEE Trans. Computers 35 (6) (1986)
Ming Huei Young, Saburo Muroga
Minimal covering problem and PLA minimization. Int. J. Parallel Program. 14 (6) (1985)
Ming Huei Young, Saburo Muroga
Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. IEEE Trans. Computers 34 (6) (1985)
Ging-Shung Yu, Saburo Muroga
Parallel multipliers with NOR gates based on G-minimum adders. Int. J. Parallel Program. 13 (2) (1984)
Akito Sakurai, Saburo Muroga
Parallel Binary Adders with a Minimum Number of Connections. IEEE Trans. Computers 32 (10) (1983)
Hung Chi Lai, Saburo Muroga
Logic Networks of Carry-Save Adders. IEEE Trans. Computers 31 (9) (1982)
Robert Brian Cutler, Saburo Muroga
Useless prime implicants of incompletely specified multiple-output switching functions. Int. J. Parallel Program. 9 (4) (1980)
Robert Brian Cutler, Saburo Muroga
Comments on "Generalization of Consensus Theory and Application to the Minimization of Boolean Functions". IEEE Trans. Computers 28 (7) (1979)
Hung Chi Lai, Saburo Muroga
Minimum Parallel Binary Adders with NOR (NAND) Gates. IEEE Trans. Computers 28 (9) (1979)
Robert Brian Cutler, Saburo Muroga
Comments on "Computing Irredundant Normal Forms from Abbreviated Presence Functions". IEEE Trans. Computers 28 (11) (1979)
Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga
Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions. IEEE Trans. Computers 28 (1) (1979)
Saburo Muroga, Hung Chi Lai
Minimization of Logic Networks Under a Generalized Cost Function. IEEE Trans. Computers 25 (9) (1976)
Hung Chi Lai, Tomoyasu Nakagawa, Saburo Muroga
Redundancy check technique for designing optimal networks by branch-and-bound method. Int. J. Parallel Program. 3 (3) (1974)
Tso-Kai Liu, Keith R. Hohulin, Lih-Er Shiau, Saburo Muroga
Optimal One-Bit Full Adders With Different Types of Gates. IEEE Trans. Computers 23 (1) (1974)
Charles R. Baugh, C. S. Chandersekaran, Richard S. Swee, Saburo Muroga
Optimal Networks of NOR-OR Gates for Functions of Three Variables. IEEE Trans. Computers 21 (2) (1972)
Toshihide Ibaraki, Tso-Kai Liu, Charles R. Baugh, Saburo Muroga
An implicit enumeration program for zero-one integer programming. Int. J. Parallel Program. 1 (1) (1972)
Saburo Muroga, Toshihide Ibaraki
Design of Optimal Switching Networks by Integer Programming. IEEE Trans. Computers 21 (6) (1972)
Toshihide Ibaraki, Saburo Muroga
Synthesis of Networks with a Minimum Number of Negative Gates. IEEE Trans. Computers 20 (1) (1971)
Charles R. Baugh, Toshihide Ibaraki, Saburo Muroga
Technical Note - Results in Using Gomory's All-Integer Integer Algorithm to Design Optimum Logic Networks. Oper. Res. 19 (4) (1971)
Saburo Muroga, Teiichi Tsuboi, Charles R. Baugh
Enumeration of Threshold Functions of Eight Variables. IEEE Trans. Computers 19 (9) (1970)
Toshihide Ibaraki, Saburo Muroga
Adaptive Linear Classifier by Linear Programming. IEEE Trans. Syst. Sci. Cybern. 6 (1) (1970)
Saburo Muroga, Iwao Toda
Lower Bound of the Number of Threshold Functions. IEEE Trans. Electron. Comput. 15 (5) (1966)
Saburo Muroga
Generation and Asymmetry of Self-Dual Threshold Functions. IEEE Trans. Electron. Comput. 14 (2) (1965)
Saburo Muroga
Lower Bounds of the Number of Threshold Functions and a Maximum Weight. IEEE Trans. Electron. Comput. 14 (2) (1965)
Saburo Muroga
Generation of self-dual threshold functions and lower bounds of the number of threshold functions and a maximum weight SWCT (1962)
Calvin C. Elgot, Saburo Muroga
Two problems on threshold functions SWCT (1961)
Saburo Muroga
Functional forms of majority functions and a necessary and sufficient condition for their realizability SWCT (1961)
Saburo Muroga, Kensuke Takashima
The Parametron Digital Computer MUSASINO-1. IRE Trans. Electron. Comput. 8 (3) (1959)
Saburo Muroga
The principle of majority decision logical elements and the complexity of their circuits. IFIP Congress (1959)
Saburo Muroga
On the capacity of a noisy continuous channel. IRE Trans. Inf. Theory 3 (1) (1957)