Yusuke Matsunaga

Publication Activity (10 Years)

Years Active: 1986-2019
Publications (10 Years): 4

Top Topics

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Yusuke Matsunaga, Masayoshi Yoshimura
An Efficient SAT-Attack Algorithm Against Logic Encryption. IOLTS (2019)
Yusuke Matsunaga
An Accelerating Technique for SAT-based ATPG. IPSJ Trans. Syst. LSI Des. Methodol. 10 (2017)
Yusuke Matsunaga
Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Yusuke Matsunaga
A Test Pattern Compaction Method Using SAT-Based Fault Grouping. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Yusuke Matsunaga
Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique. ASP-DAC (2015)
Yusuke Matsunaga
Synthesis algorithm of parallel index generation units. DATE (2014)
Yusuke Matsunaga
Synthesis Algorithm for Parallel Index Generator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
An Exact Approach for GPC-Based Compressor Tree Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Inf. Media Technol. 7 (2) (2012)
Taiga Takata, Yusuke Matsunaga
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5 (2012)
Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5 (2012)
Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS (2012)
Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS (2011)
Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT (2011)
Taiga Takata, Yusuke Matsunaga
A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. IOLTS (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Multi-Operand Adder Synthesis Targeting FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ISLPED (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Multi-operand adder synthesis on FPGAs using generalized parallel counters. ASP-DAC (2010)
Taiga Takata, Yusuke Matsunaga
A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). FPGA (2010)
Taiga Takata, Yusuke Matsunaga
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI (2009)
Taiga Takata, Yusuke Matsunaga
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Sho Kodama, Yusuke Matsunaga
Binding Refinement for Multiplexer Reduction. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Taiga Takata, Yusuke Matsunaga
Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Synthesis of parallel prefix adders considering switching activities. ICCD (2008)
Tsuyoshi Sadakata, Yusuke Matsunaga
A Behavioral Synthesis Method with Special Functional Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Taiga Takata, Yusuke Matsunaga
Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC (2008)
Makoto Sugihara, Yusuke Matsunaga, Kazuaki J. Murakami
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Tsuyoshi Sadakata, Yusuke Matsunaga
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis. ASP-DAC (2008)
Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki J. Murakami
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Trans. Electron. (5) (2007)
Taeko Matsunaga, Yusuke Matsunaga
Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI (2007)
Tsuyoshi Sadakata, Yusuke Matsunaga
A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2007)
Yusuke Matsunaga
Special Section on VLSI Design and CAD Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Taeko Matsunaga, Yusuke Matsunaga
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Yusuke Matsunaga
Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2007)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS (2006)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. (3) (2006)
Masayoshi Yoshimura, Yusuke Matsunaga
Development of practical ATPG tool with flexible interface. ATS (2006)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC (2005)
Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI (2004)
Hiroyuki Higuchi, Yusuke Matsunaga
Enhancing the performance of multi-cycle path analysis in an industrial setting. ASP-DAC (2004)
Ei Ando, Masafumi Yamashita, Toshio Nakata, Yusuke Matsunaga
The statistical longest path problem and its application to delay analysis of logical circuits. Timing Issues in the Specification and Synthesis of Digital Systems (2002)
Yusuke Matsunaga
An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Yusuke Matsunaga
On accelerating pattern matching for technology mapping. ICCAD (1998)
Hiroyuki Higuchi, Yusuke Matsunaga
A Fast State Reduction Algorithm for Incompletely Specified Finite State Machines. DAC (1996)
Yusuke Matsunaga
An Efficient Equivalence Checker for Combinational Circuits. DAC (1996)
Yusuke Matsunaga
A New Algorithm for Boolean Matching Utilizing Structural Information. IEICE Trans. Inf. Syst. (3) (1995)
Hiroyuki Higuchi, Yusuke Matsunaga
Implicit prime compatible generation for minimizing incompletely specified finite state machines. ASP-DAC (1995)
Yutaka Tamiya, Yusuke Matsunaga, Masahiro Fujita
LP based cell selection with constraints of timing, area, and power consumption. ICCAD (1994)
Masahiro Fujita, Hisanori Fujisawa, Yusuke Matsunaga
Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (1) (1993)
Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton
On Computing the Transitive Closure of a State Transition Relation. DAC (1993)
Masahiro Fujita, Yusuke Matsunaga
Multi-Level Logic Minimization Based on Minimal Support and its Application to the Minimization of Look-Up Table Type FPGAs. ICCAD (1991)
Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
A Resynthesis Approach for Network Optimization. DAC (1991)
Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis. EURO-DAC (1991)
Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda
Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. ICCAD (1990)
Hitomi Sato, Yoshihiro Yasue, Yusuke Matsunaga, Masahiro Fujita
Boolean Resubstitution with Permissible Functions and Binary Decision Diagrams. DAC (1990)
Hitomi Sato, Norikazu Takahashi, Yusuke Matsunaga, Masahiro Fujita
Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams. ICCD (1990)
Yusuke Matsunaga, Masahiro Fujita, Takeo Kakuda
Multi-Level Logic Minimization Across Latch Boundaries. ICCAD (1990)
Yusuke Matsunaga, Masahiro Fujita
Multi-level logic optimization using binary decision diagrams. ICCAD (1989)
Fumihiro Maruyama, Taeko Kakuda, Yusuke Matsunaga, Yoriko Minoda, Shuho Sawada, Nobuaki Kawato
co-LODEX: A Cooperative Expert System for Logic design. FGCS (1988)
Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)