Masayoshi Yoshimura

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 17

Top Topics

Matlab Simulation

Evolvable Hardware

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (3) (2024)
Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage. DFT (2023)
Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing. DFT (2023)
Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers. DFT (2023)
Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level. DFT (2022)
Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT. DFT (2020)
Toshinori Hosokawa, Kenichiro Misawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai
A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method. IOLTS (2020)
Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura
A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths. IOLTS (2019)
Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai
A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively. DFT (2019)
Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa
A State Assignment Method to Improve Transition Fault Coverage for Controllers. DFT (2019)
Yusuke Matsunaga, Masayoshi Yoshimura
An Efficient SAT-Attack Algorithm Against Logic Encryption. IOLTS (2019)
Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura
A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns. IOLTS (2018)
Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura
A Capture Safe Static Test Compaction Method Based on Don't Cares. IOLTS (2018)
Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification. IOLTS (2018)
Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa
A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura
Controller augmentation and test point insertion at RTL for concurrent operational unit testing. IOLTS (2017)
Masayoshi Yoshimura, Tomohiro Bouyashiki, Toshinori Hosokawa
A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations. PRDC (2017)
Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa
A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions. ATS (2015)
Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura
A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution. IEICE Trans. Inf. Syst. (9) (2013)
Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa
A smart Trojan circuit and smart attack method in AES encryption circuits. DFTS (2013)
Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura
A don't care identification method for test compaction. DDECS (2013)
Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. Inf. Media Technol. 7 (2) (2012)
Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
An Exact Estimation Algorithm of Error Propagation Probability for Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5 (2012)
Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki J. Murakami
Methodology for early estimation of hierarchical routing resources in 3D FPGAs. VLSI-SoC (2012)
Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS (2012)
Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS (2011)
Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga
A Soft Error Tolerance Estimation Method for Sequential Circuits. DFT (2011)
Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki
Evaluation of transition untestable faults using a multi-cycle capture test generation method. DDECS (2010)
Masayoshi Yoshimura, Yusuke Matsunaga
Development of practical ATPG tool with flexible interface. ATS (2006)
Masayoshi Yoshimura
Implementation of Multiobjective Optimization Procedures at the Product Design Planning Stage. System Modelling and Optimization (2005)
Atsushi Kitazawa, Masayoshi Yoshimura
SemanticObjects and Biomedical Informatics. BIBE (2004)
Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta
A Test Point Insertion Method to Reduce the Number of Test Patterns. Asian Test Symposium (2002)
Masayoshi Yoshimura
Collaborative optimization for product design and manufacturing. CAD (2002)
Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta
Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. ASP-DAC (2001)