Taiga Takata

Publication Activity (10 Years)

Years Active: 2005-2013
Publications (10 Years): 0

Top Topics

Information Loss

Expectation Maximization

Simulated Annealing

Analytical Model

Top Venues

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga
Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Taiga Takata, Yusuke Matsunaga
A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. IPSJ Trans. Syst. LSI Des. Methodol. 5 (2012)
Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS (2011)
Taiga Takata, Yusuke Matsunaga
A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits. IOLTS (2011)
Taiga Takata, Yusuke Matsunaga
A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). FPGA (2010)
Taiga Takata, Yusuke Matsunaga
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI (2009)
Taiga Takata, Yusuke Matsunaga
Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Taiga Takata, Yusuke Matsunaga
Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Taiga Takata, Yusuke Matsunaga
Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. ASP-DAC (2008)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS (2006)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. (3) (2006)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC (2005)