Makoto Sugihara

Publication Activity (10 Years)

Years Active: 1998-2014
Publications (10 Years): 0

Top Topics

Geometric Constraints

Constraint Violations

Constrained Minimization

Top Venues

IEICE Trans. Inf. Syst.

Publications

Makoto Sugihara
Minimization of the Fabrication Cost for a Bridged-Bus-Based TDMA System under Hard Real-Time Constraints. IEICE Trans. Inf. Syst. (12) (2014)
Makoto Sugihara, Akihito Iwanaga
Minimization of FlexRay Bus Bandwidth for Hard Real-Time Applications. Inf. Media Technol. 8 (1) (2013)
Makoto Sugihara, Akihito Iwanaga
Slot Multiplexing Optimization for Minimizing the Operating Frequency of a FlexRay Bus under Hard Real-time Constraints. Inf. Media Technol. 8 (3) (2013)
Makoto Sugihara, Akihito Iwanaga
Minimization of FlexRay Bus Bandwidth for Hard Real-Time Applications. J. Inf. Process. 21 (1) (2013)
Makoto Sugihara, Akihito Iwanaga
Slot Multiplexing Optimization for Minimizing the Operating Frequency of a FlexRay Bus under Hard Real-time Constraints. J. Inf. Process. 21 (3) (2013)
Makoto Sugihara
A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors. IEICE Trans. Electron. (4) (2011)
Makoto Sugihara
Character-Size Optimization for Reducing the Number of EB Shots of MCC Lithographic Systems. IEICE Trans. Electron. (5) (2010)
Makoto Sugihara
Dynamic Control Flow Checking Technique for Reliable Microprocessors. DSD (2010)
Makoto Sugihara
On Synthesizing a Reliable Multiprocessor for Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Makoto Sugihara
Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints. DSD (2009)
Makoto Sugihara
Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems. IEICE Trans. Electron. (4) (2008)
Makoto Sugihara
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems. ISQED (2008)
Makoto Sugihara, Yusuke Matsunaga, Kazuaki J. Murakami
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
Task scheduling for reliable cache architectures of multiprocessor systems. DATE (2007)
Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki J. Murakami
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography. IEICE Trans. Electron. (5) (2007)
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems. IEICE Trans. Electron. (10) (2007)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
A character size optimization technique for throughput enhancement of character projection lithography. ISCAS (2006)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. IEICE Trans. Electron. (3) (2006)
Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto
A Simulation-Based Soft Error Estimation Methodology for Computer Systems. ISQED (2006)
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. SoC (2005)
Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints. ISVLSI (2004)
Makoto Sugihara, Hiroto Yasuura
Optimization of Test Accesses with a Combined BIST and External Test Scheme. VLSI Design (2002)
Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE (2000)
Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores. PDPTA (2000)
Makoto Sugihara, Hiroshi Date, Hiroto Yasuura
A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC (1998)