Hiroto Yasuura

ORCID

Publication Activity (10 Years)

Years Active: 1981-2017
Publications (10 Years): 1

Top Venues

ASP-DAC

Publications

Hiroto Yasuura
ASP-DAC 2017 keynote speech I-3: Design of society: Beyond digital system design. ASP-DAC (2017)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
A Selective Replacement Method for Timing-Error-Predicting flip-Flops. J. Circuits Syst. Comput. 21 (6) (2012)
Atsushi Shimada, Shigeru Takano, Shigeaki Tagashira, Rin-Ichiro Taniguchi, Hiroto Yasuura
WiP Abstract: Estimation of Electric Power Consumption of Individuals by Observing People's Activity. ICCPS (2012)
Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS (2012)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida
Guidelines for mitigating NBTI degradation in on-chip memories. ISCIT (2012)
Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS (2011)
Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura
Towards Modeling Stored-value Electronic Money Systems. Inf. Media Technol. 6 (1) (2011)
Toru Nakamura, Shunsuke Inenaga, Kensuke Baba, Daisuke Ikeda, Hiroto Yasuura
An Anonymous Authentication Protocol with Single-database PIR. AISC (2011)
Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura
Password Based Anonymous Authentication with Private Information Retrieval. J. Digit. Inf. Manag. 9 (2) (2011)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. IEICE Trans. Electron. (4) (2011)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
Signal probability control for relieving NBTI in SRAM cells. ISQED (2010)
Yuji Kunitake, Toshinori Sato, Hiroto Yasuura
A Replacement Strategy for Canary Flip-Flops. PRDC (2010)
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J. Signal Process. Syst. 60 (2) (2010)
Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Kensuke Baba, Hiroto Yasuura
An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services. ICCSA (4) (2010)
Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura
An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP (2010)
Ashir Ahmed, Lutfe Kabir, Hiroto Yasuura
An Information Platform for Low-Literate Villagers. AINA (2010)
Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Trans. Electron. (4) (2009)
Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe
Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC (2009)
Shunsuke Inenaga, Kenichirou Oyama, Hiroto Yasuura
Towards Modeling Stored-value Electronic Money Systems. NaBIC (2009)
Tomomi Yamasaki, Shunsuke Inenaga, Daisuke Ikeda, Hiroto Yasuura
Modeling Costs of Access Control with Various Key Management Systems. PDPTA (2009)
Noriaki Sakamoto, Mitsuaki Fukase, Tsunenori Mine, Shigeru Kusakabe, Tsuneo Nakanishi, Yoichi Omori, Mohammad Mesbah Uddin, Keijiro Araki, Akira Fukuda, Hiroto Yasuura, Teruaki Kitasuka
Large Scale Business-academia Collaboration in Master Education Course. CSEDU (2) (2009)
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
An Optimization Technique for Low-Energy Embedded Memory Systems. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
variation. Microelectron. J. 39 (12) (2008)
Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI (2008)
Shinsuke Ohtsuka, Satoshi Kawamoto, Shigeru Takano, Kensuke Baba, Hiroto Yasuura
A Note on Biometrics-based Authentication with Portable Device. SECRYPT (2008)
Mohammad Mesbah Uddin, Salahuddin Muhammad Salim Zabir, Yasunobu Nohara, Hiroto Yasuura
A Framework of Authentic Post-Issuance Program Modification for Multi-Application Smart Cards. ICWN (2008)
Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS (2008)
Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura
A Secure High-Speed Identification Scheme for RFID Using Bloom Filters. ARES (2008)
Mohammad Mesbah Uddin, Yasunobu Nohara, Daisuke Ikeda, Hiroto Yasuura
A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2008)
Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura
Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTIMedia (2007)
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC (2007)
Adil El Bourichi, Hiroto Yasuura
A low complexity and energy efficient dynamic channel allocation algorithm for multiuser OFDM. WTS (2007)
Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura
Unlinkability and Real World Constraints in RFID Systems. PerCom Workshops (2007)
Tomomi Yamasaki, Toru Nakamura, Kensuke Baba, Hiroto Yasuura
A Door Access Control System with Mobile Phones. PWC (2007)
Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah
An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia (2006)
Takahiro Watanabe, Yasunobu Nohara, Kensuke Baba, Sozo Inoue, Hiroto Yasuura
On Authentication between Human and Computer. PerCom Workshops (2006)
Yasunobu Nohara, Toru Nakamura, Kensuke Baba, Sozo Inoue, Hiroto Yasuura
Unlinkable Identification for Large-scale RFID Systems. Inf. Media Technol. 1 (2) (2006)
Sozo Inoue, Hiroto Yasuura, Daisuke Hagiwara
Systematic Error Detection for RFID Reliability. ARES (2006)
Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, Jun Sasaki, Yasushi Aoki, Kazumi Akimoto
An RFID-based multi-service system for supporting conference events. AMT (2005)
Kosuke Tarumi, Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura
Bitwidth Optimization for Low Power Digital FIR Filter Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Yasunobu Nohara, Sozo Inoue, Kensuke Baba, Hiroto Yasuura
Quantitative evaluation of unlinkable ID matching schemes. WPES (2005)
Hiroto Yasuura, Shoji Kawahito
Special Section on Papers Selected from AP-ASIC 2004. IEICE Trans. Electron. (8) (2005)
Masanori Muroyama, Kosuke Tarumi, Koji Makiyama, Hiroto Yasuura
A variation-aware low-power coding methodology for tightly coupled buses. ASP-DAC (2005)
Yasunobu Nohara, Sozo Inoue, Hiroto Yasuura
Toward Unlinkable ID Management for Multi-Service Environments. PerCom Workshops (2005)
Hiroto Yasuura
Digitally Named World: Challenges for New Social Infrastructures. ISQED (2004)
Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
Routing methodology for minimizing 1nterconnect energy dissipation. ACM Great Lakes Symposium on VLSI (2003)
Masanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura
A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits. DSD (2003)
Takashi Yamada, Takeshi Sakamoto, Shinji Furuichi, Mamoru Mukuno, Yoshifumi Matsushita, Hiroto Yasuura
Pre-Route Power Analysis Techniques for SoC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2003)
Yun Cao, Hiroto Yasuura
Leakage Power Reduction for Battery-Operated Portable Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
Reduction of crosstalk noise by optimizing 3-D configuration of the routing grid. ASP-DAC (2003)
Akihiko Hyodo, Masanori Muroyama, Hiroto Yasuura
Variable Pipeline Depth Processor for Energy Efficient Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
Hiroto Yasuura
Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information Technologies. DSD (2003)
Takashi Yamada, Atsushi Sakai, Yoshifumi Matsushita, Hiroto Yasuura
Routing Methodology for Minimizing Crosstalk in SoC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2003)
Yun Cao, Hiroto Yasuura
Quality-driven design by bitwidth optimization for video applications. ASP-DAC (2003)
Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
Special Session: Security on SoC. ISSS (2002)
Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS (2002)
Makoto Sugihara, Hiroto Yasuura
Optimization of Test Accesses with a Combined BIST and External Test Scheme. VLSI Design (2002)
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA. DSD (2002)
Yun Cao, Hiroto Yasuura
Quality-Driven Design for Video Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Takeshi Sakamoto, Takashi Yamada, Mamoru Mukuno, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
Power analysis techniques for SoC with improved wiring models. ISLPED (2002)
Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura
A Power Minimization Technique for Arithmetic Circuits by Cell Selection. VLSI Design (2002)
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems. ISSS (2002)
Takanori Okuma, Yun Cao, Masanori Muroyama, Hiroto Yasuura
Reducing access energy of on-chip data memory considering active data bitwidth. ISLPED (2002)
Shoji Goto, Takashi Yamada, Norihisa Takayama, Yoshifumi Matsushita, Yasoo Harada, Hiroto Yasuura
A low-power digital matched filter for spread-spectrum systems. ISLPED (2002)
Barry Shackleford, Greg Snider, Richard J. Carter, Etsuko Okushi, Mitsuhiro Yasuda, Katsuhiko Seo, Hiroto Yasuura
A High-Performance, Pipelined, FPGA-Based Genetic Algorithm Machine. Genet. Program. Evolvable Mach. 2 (1) (2001)
Takanori Okuma, Hiroto Yasuura, Tohru Ishihara
Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Des. Test Comput. 18 (2) (2001)
Yun Cao, Hiroto Yasuura
A system-level energy minimization approach using datapath width optimization. ISLPED (2001)
Hiroto Yasuura
Editorial. Des. Autom. Embed. Syst. 5 (2) (2000)
Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura
Flexible System LSI for Embedded Systems and Its Optimization Techniques. Des. Autom. Embed. Syst. 5 (2) (2000)
Kei Hirose, Hiroto Yasuura
A Bus Delay Reduction Technique Considering Crosstalk. DATE (2000)
Hajime Yamashita, Hiroto Yasuura, Eko Fajar, Yun Cao
Variable size analysis and validation of computation quality. HLDVT (2000)
Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. DATE (2000)
Tohru Ishihara, Hiroto Yasuura
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE (2000)
Victor M. Goulart Ferreira, Hiroto Yasuura
Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-Offs. SBCCI (2000)
Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura
One language or more?: how can we design an SoC at a system level? ASP-DAC (2000)
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
An FPGA-based genetic algorithm machine (poster abstract). FPGA (2000)
Takanori Okuma, Tohru Ishihara, Hiroto Yasuura
Real-Time Task Scheduling for a Variable Voltage Processor. ISSS (1999)
Hiroyuki Tomiyama, Hiroto Yasuura
Module Selection Using Manufacturing Information. ASP-DAC (1998)
Makoto Sugihara, Hiroshi Date, Hiroto Yasuura
A novel test methodology for core-based system LSIs and a testing time minimization problem. ITC (1998)
Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura
Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE (1998)
Tohru Ishihara, Hiroto Yasuura
Power-Pro: Programmable Power Management Architecture. ASP-DAC (1998)
Tohru Ishihara, Hiroto Yasuura
Voltage scheduling problem for dynamically variable voltage processors. ISLPED (1998)
Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura
Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS (1998)
Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura
Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS (1998)
Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar
Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. 14 (3) (1998)
Hiroyuki Tomiyama, Hiroto Yasuura
Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. 2 (4) (1997)
Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura
A High-Performance Hardware Implementation of a Survival-Based Genetic Algorithm. ICONIP (1) (1997)
Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura
Memory-CPU Size Optimization for Embedded System Designs. DAC (1997)
Fumio Suzuki, Hisao Koizumi, M. Hiramine, K. Yamamoto, Hiroto Yasuura, K. Okino
A HW/SW co-design environment for multi-media equipments development using inverse problem. CODES (1997)
Hiroyuki Tomiyama, Hiroto Yasuura
Optimal Code Placement of Embedded Software for Instruction Caches. ED&TC (1996)
Hiroyuki Tomiyama, Hiroto Yasuura
Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS (1996)
Tohru Ishihara, Hiroto Yasuura
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED (1996)
Tetsuya Yamada, Hiroto Yasuura
On the Computational Power of Binary Decision Diagram with Redundant Variables. Formal Methods Syst. Des. 8 (1) (1996)
Hisao Koizumi, Katsuhiko Seo, Fumio Suzuki, Yoshisuke Ohtsuru, Hiroto Yasuura
A Proposal for a Co-design Method in Control Systems Using Combination of Models. IEICE Trans. Inf. Syst. (3) (1995)
Hiroto Yasuura
Foreword. IEICE Trans. Inf. Syst. (3) (1995)
Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura
Design Reuse: Fact or Fiction? (Panel). DAC (1994)
Takashi Hashimoto, Kazuaki J. Murakami, Tetsuo Hironaka, Hiroto Yasuura
A Micro-Vectorprocessor Architecture: Performance Modeling and Benchmarking. International Conference on Supercomputing (1993)
Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura
Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits (1992)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hiroto Yasuura