Srivaths Ravi

ORCID

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 15

Top Venues

Publications

Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing. J. Electron. Test. 39 (1) (2023)
Praise O. Farayola, Ekaniyere Oko-Odion, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction. IEEE Des. Test 40 (5) (2023)
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing. DFT (2022)
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing. J. Electron. Test. 38 (6) (2022)
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing. ITC (2022)
Abraham Steenhoek, Praise O. Farayola, Isaac Bruce, Shravan Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Graph Theory Approach for Multi-site ATE Board Parameter Extraction. ETS (2022)
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
The Least-Squares Approach to Systematic Error Identification and Calibration in Semiconductor Multisite Testing. VTS (2022)
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Systematic Hardware Error Identification and Calibration for Massive Multisite Testing. ITC (2021)
Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Detection of Site to Site Variations From Volume Measurement Data in Multisite Semiconductor Testing. IEEE Trans. Instrum. Meas. 70 (2021)
Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Massive Multisite Variability-Aware Die Distribution Estimation for Analog/Mixed-Signal Circuits Test Validation. DTIS (2021)
Isaac Bruce, Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study. ETS (2021)
Praise O. Farayola, Shravan K. Chaganti, Abdullah O. Obaidi, Abalhassan Sheikh, Srivaths Ravi, Degang Chen
Quantile - Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing. VTS (2020)
V. Prasanth, David Foley, Srivaths Ravi
Demystifying automotive safety and security for semiconductor developer. ITC (2017)
Yiorgos Makris, Srivaths Ravi, Amit Majumdar
Foreword. VTS (2017)
Prabhat Mishra, Swarup Bhunia, Srivaths Ravi
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems. VLSI Design (2015)
Raashid Shaikh, Pradeep Wilson, Khushboo Agarwal, H. V. Sanjay, Rajesh Tiwari, Kaushik Lath, Srivaths Ravi
At-speed capture power reduction using layout-aware granular clock gate enable controls. ITC (2014)
Chandan Kumar, Fadi Maamari, Kiran Vittal, Wilson Pradeep, Rajesh Tiwari, Srivaths Ravi
Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs. ATS (2014)
Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula
Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices. VLSI Design (2014)
Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test. J. Low Power Electron. 7 (4) (2011)
Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi
Multi-CoDec Configurations for Low Power and High Quality Scan Test. VLSI Design (2011)
Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe
Methodology for early and accurate test power estimation at RTL. ITC (2010)
Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji
A generic low power scan chain wrapper for designs using scan compression. VTS (2010)
George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures. J. Low Power Electron. 5 (1) (2009)
Anish Muttreja, Srivaths Ravi, Niraj K. Jha
Variability-Tolerant Register-Transfer Level Synthesis. VLSI Design (2008)
Khushboo Agarwal, Srinivas Vooka, Srivaths Ravi, Rubin A. Parekhji, Arjun Singh Gill
Power Analysis and Reduction Techniques for Transition Fault Testing. ATS (2008)
Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, Michail Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
Systematic Software-Based Self-Test for Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. 16 (11) (2008)
Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. VTS (2008)
Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena
Low Power Test for Nanometer System-on-Chips (SoCs). J. Low Power Electron. 4 (1) (2008)
Srivaths Ravi, Stefan Mangard
Tutorial T1: Designing Secure SoCs. VLSI Design (2007)
Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Energy and execution time analysis of a software-based trusted platform module. DATE (2007)
Srivaths Ravi
Power-aware test: Challenges and solutions. ITC (2007)
Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. Very Large Scale Integr. Syst. 15 (4) (2007)
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 15 (11) (2007)
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (11) (2007)
Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 15 (3) (2007)
Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. Very Large Scale Integr. Syst. 15 (6) (2007)
Joel Coburn, Srivaths Ravi, Anand Raghunathan
Hardware Accelerated Power Estimation CoRR (2007)
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (10) (2007)
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embed. Comput. Syst. 7 (1) (2007)
Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji
Methodology for low power test pattern generation using activity threshold control logic. ICCAD (2007)
Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
Systematic software-based self-test for pipelined processors. DAC (2006)
Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (3) (2006)
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. 5 (2) (2006)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Architectures for efficient face authentication in embedded systems. DATE Designers' Forum (2006)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee
Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum (2006)
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Active Learning Driven Data Acquisition for Sensor Networks. ISCC (2006)
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design (2006)
Gang Tan, Andrew W. Appel, Srimat Chakradhar, Anand Raghunathan, Srivaths Ravi, Daniel C. Wang
Safe Java Native Interface. ISSSE (2006)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design (2006)
Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 14 (12) (2006)
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Architectural support for safe software execution on embedded processors. CODES+ISSS (2006)
Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC (2006)
Joel Coburn, Srivaths Ravi, Anand Raghunathan
Power emulation: a new paradigm for power estimation. DAC (2005)
Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
SECA: security-enhanced communication architecture. CASES (2005)
Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE (2005)
Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design (2005)
Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS (2005)
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Hybrid simulation for embedded software energy estimation. DAC (2005)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design (2005)
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. CICC (2005)
Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Efficient fingerprint-based user authentication for embedded systems. DAC (2005)
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (11) (2005)
Joel Coburn, Srivaths Ravi, Anand Raghunathan
Hardware Accelerated Power Estimation. DATE (2005)
Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Power estimation for cycle-accurate functional descriptions of hardware. ICCAD (2004)
Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady
Security in embedded systems: Design challenges. ACM Trans. Embed. Comput. Syst. 3 (3) (2004)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (2) (2004)
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
A hybrid energy-estimation technique for extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (5) (2004)
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
High-level synthesis using computation-unit integrated memories. ICCAD (2004)
Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan
Security as a new dimension in embedded system design. DAC (2004)
Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
Tamper Resistance Mechanisms for Secure, Embedded Systems. VLSI Design (2004)
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design (2004)
Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha
Automated energy/performance macromodeling of embedded software. DAC (2004)
Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD (2003)
Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. DATE (2003)
Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
Efficient RTL Power Estimation for Large Designs. VLSI Design (2003)
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD (2003)
Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater
Securing Mobile Appliances: New Challenges for the System Designer. DATE (2003)
Indradeep Ghosh, Srivaths Ravi
On automatic generation of RTL validation test benches using circuit testing techniques. ACM Great Lakes Symposium on VLSI (2003)
Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar
Embedding Security in Wireless Embedded Systems. VLSI Design (2003)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
A Scalable Application-Specific Processor Synthesis Methodology. ICCAD (2003)
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey
A scalable software-based self-test methodology for programmable processors. DAC (2003)
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Analyzing the energy consumption of security protocols. ISLPED (2003)
Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Energy Estimation for Extensible Processors. DATE (2003)
Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys
Special Session: Security on SoC. ISSS (2002)
Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
High-level synthesis of distributed logic-memory architectures. ICCAD (2002)
Jacob Chang, Srivaths Ravi, Anand Raghunathan
FLEXBAR: A crossbar switching fabric with improved performance and utilization. CICC (2002)
Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi
Securing Wireless Data: System Architecture Challenges. ISSS (2002)
Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana
Optimizing public-key encryption for wireless clients. ICC (2002)
Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass
System design methodologies for a wireless security processing platform. DAC (2002)
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha
High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (7) (2002)
Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
Synthesis of custom processors based on extensible platforms. ICCAD (2002)
Srivaths Ravi, Niraj K. Jha
Test synthesis of systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (10) (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Srivaths Ravi