V. R. Devanathan

Publication Activity (10 Years)

Years Active: 2003-2016
Publications (10 Years): 1

Top Topics

Compute Intensive

General Purpose Processors

Application Specific

Top Venues

J. Low Power Electron.

ACM J. Emerg. Technol. Comput. Syst.

Publications

V. R. Devanathan, Sumant Kale
A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath. ITC (2016)
Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. 11 (2) (2015)
Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. VLSI Design (2015)
Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. 12 (3) (2015)
V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji
New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. VLSI Design (2015)
Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSI Design (2014)
Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji
Towards adaptive test of multi-core RF SoCs. DATE (2013)
Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. 9 (2) (2013)
Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. 8 (5) (2012)
V. R. Devanathan, Srinivas Kumar Vooka
Techniques to improve memory interface test quality for complex SoCs. ITC (2011)
V. R. Devanathan, Ishaan Santhosh Shah
Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test. VLSI Design (2011)
V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra
Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. Asian Test Symposium (2011)
V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar
Towards effective and compression-friendly test of memory interface logic. ITC (2010)
M. A. Maluk Mohamed, V. R. Devanathan, D. Janakiram
EOMP: an exactly once multicast protocol for distributed mobile systems. Int. J. Parallel Emergent Distributed Syst. 25 (3) (2010)
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. 4 (1) (2008)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design (2007)
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. 24 (4) (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS (2007)
Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji
Methodology for low power test pattern generation using activity threshold control logic. ICCAD (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. 2 (3) (2006)
C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar
A Framework for Distributed and Hierarchical Design-for-Test. VLSI Design (2005)
V. R. Devanathan
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. Asian Test Symposium (2005)
D. Janaki Ram, M. A. Maluk Mohamed, V. R. Devanathan
A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems. ICDCS Workshops (2003)