C. P. Ravikumar

Publication Activity (10 Years)

Years Active: 1987-2020
Publications (10 Years): 3

Top Venues

J. Low Power Electron.

CoRR

IOLTS

Publications

C. P. Ravikumar
Industrial Practices in Low-Power Robust Design. IOLTS (2020)
Ananya Ravikumar, C. P. Ravikumar
Architectural Optimization of Hierarchically Organized Wireless Sensor Networks for Energy, Cost, and Security. J. Low Power Electron. 14 (1) (2018)
C. P. Ravikumar
Smart and Fault-Tolerant LED-Based Street Lamps. J. Low Power Electron. 12 (3) (2016)
Namita Sharma, Vineet Sahula, C. P. Ravikumar
Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation CoRR (2013)
T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip. ACM Trans. Embed. Comput. Syst. 11 (1) (2012)
C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen
Test Strategies for Low Power Devices. DATE (2008)
C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen
Test Strategies for Low-Power Devices. J. Low Power Electron. 4 (2) (2008)
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
Memory Architecture Exploration Framework for Cache Based Embedded SOC. VLSI Design (2008)
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. 4 (1) (2008)
Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. VLSI Design (2008)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design (2007)
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. VLSI Design (2007)
V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC (2007)
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. ASP-DAC (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. 24 (4) (2007)
Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS (2007)
Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (5) (2007)
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar
A critical-path-aware partial gating approach for test power reduction. ACM Trans. Design Autom. Electr. Syst. 12 (2) (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS (2007)
C. P. Ravikumar, Jari Nurmi
Conference Reports. IEEE Des. Test Comput. 24 (2) (2007)
Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy
Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electron. 3 (1) (2007)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC (2007)
Mitra Subhasish, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar
Conference Reports. IEEE Des. Test Comput. 23 (4) (2006)
V. R. Devanathan, C. P. Ravikumar, V. Kamakoti
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. 2 (3) (2006)
C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar
A Framework for Distributed and Hierarchical Design-for-Test. VLSI Design (2005)
Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. ITC (2005)
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar
Partial Gating Optimization for Power Reduction During Test Application. Asian Test Symposium (2005)
Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
At-Speed Transition Fault Testing With Low Speed Scan Enable. VTS (2005)
Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar
Enhanced launch-off-capture transition fault testing. ITC (2005)
Aman Kokrady, C. P. Ravikumar
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. VLSI Design (2004)
Mohammed Fadle Abdulla, C. P. Ravikumar
A self-checking signature scheme for checking backdoor security attacks in Internet. J. High Speed Networks 13 (4) (2004)
C. P. Ravikumar
Multiprocessor Architectures for Embedded System-on-chip Applications. VLSI Design (2004)
C. P. Ravikumar, Graham Hetherington
A Holistic Parallel and Hierarchical Approach towards Design-For-Test. ITC (2004)
T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar
Optimal Code and Data Layout in Embedded Systems. VLSI Design (2003)
C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra
Mutual Testing based on Wavelet Transforms. VLSI Design (2003)
Aman Kokrady, C. P. Ravikumar
Static Verification of Test Vectors for IR Drop Failure. ICCAD (2003)
Mirza Mohd. Sufyan Beg, C. P. Ravikumar
Measuring the Quality of Web Search Results. JCIS (2002)
Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri
Improvement of ASIC Design Processes. VLSI Design (2002)
C. P. Ravikumar, Rahul Kumar
Divide-and-Conquer IDDQ Testing for Core-Based System Chips. VLSI Design (2002)
Rahul Kumar, C. P. Ravikumar
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. VLSI Design (2002)
Shampa Chakraverty, C. P. Ravikumar, D. Roy Choudhuri
An Evolutionary Scheme for Cosynthesis of Real-Time Systems. VLSI Design (2002)
Vishal Dalal, C. P. Ravikumar
Software Power Optimizations In An Embedded System. VLSI Design (2001)
C. P. Ravikumar, Vikas Jain, Anurag Dod
Distributed Fault Simulation Algorithms on Parallel Virtual Machine. VLSI Design 2001 (1) (2001)
Vineet Sahula, C. P. Ravikumar
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. VLSI Design (2001)
V. Sankara Subramanian, C. P. Ravikumar
Estimating Crosstalk From Vlsi Layouts. VLSI Design (2001)
Shampa Chakraverty, C. P. Ravikumar
A Stochastic Framework for Co-synthesis of Real-Time Systems. LCTES (2000)
Anil Sharma, C. P. Ravikumar
Efficient Implementation of ADPCM Codec. VLSI Design (2000)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
A scheme for multiple on-chip signature checking for embedded SRAMS. J. Syst. Archit. 46 (2) (2000)
C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. VLSI Design (2000)
Rajesh Kannah, C. P. Ravikumar
Functional Testing of Microprocessors with Graded Fault Coverage. Asian Test Symposium (2000)
C. P. Ravikumar, Meeta Sharma, Prachi Jain
Design of WDM Networks for Delay-Bound Multicasting. HiPC (1999)
C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. Asian Test Symposium (1999)
Nishit Narang, Girish Kumar, C. P. Ravikumar
Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications. HiPC (1999)
C. P. Ravikumar
High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications. Scalable Comput. Pract. Exp. 2 (4) (1999)
C. P. Ravikumar, Ajay Mittal
Hierarchical Delay Fault Simulation. VLSI Design (1999)
C. P. Ravikumar, Manish Sharma, R. K. Patney
Improving the Diagnosability of Digital Circuits. VLSI Design (1999)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
Built-in Self Test Based on Multiple On-Chip Signature Checking. J. Electron. Test. 14 (3) (1999)
Rohit Sharma, C. P. Ravikumar
Design Issues in Synthesis of Reusable Cores. Great Lakes Symposium on VLSI (1999)
C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal
A functional-level testability measure for register-level circuits and its estimation. Microprocess. Microsystems 22 (9) (1999)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. J. Electron. Test. 12 (3) (1998)
Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar
Freedom: Statistical Behavioral Estimation of System Energy and Power. VLSI Design (1998)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
Hybrid Testing Schemes Based on Mutual and Signature Testing. VLSI Design (1998)
Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar
An Evolutionary Approach to System Redesign. VLSI Design (1998)
Girish Kumar, Nishit Narang, C. P. Ravikumar
Efficient algorithms for delay-bounded minimum cost path problem in communication networks. HiPC (1998)
Nidhi Agrawal, C. P. Ravikumar
Adaptive Routing Based on Deadlock Recovery. Euro-Par (1998)
C. P. Ravikumar, Nikhil Sharma
Testability-Driven Layout of Combinational Circuits. VLSI Design 1998 (4) (1998)
Roman Trobec, C. P. Ravikumar
Parallel Methods for Vlsi Layout Design. IEEE Concurr. 6 (1) (1998)
C. P. Ravikumar, N. Satya Prasad
Evaluating BIST Architectures for Low Power. Asian Test Symposium (1998)
C. P. Ravikumar, Dilip R. Pandit, Anubhav Mishra
Performance-driven design and redesign of high-speed local area networks. HiPC (1998)
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
Synthesis of Testable RTL Designs. VLSI Design (1998)
C. P. Ravikumar, Hemant Joshi
SCOAP-based Testability Analysis from Hierarchical Netlists. VLSI Design 1998 (2) (1998)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
On-Chip Signature Checking for Embedded Memories. VLSI Design (1998)
C. P. Ravikumar, Rajneesh Bajpai
Source-based delay-bounded multicasting in multimedia networks. Comput. Commun. 21 (2) (1998)
C. P. Ravikumar, Vikas Jain, Anurag Dod
Faster Fault Simulation Through Distributed Computing. VLSI Design (1997)
Nidhi Agrawal, C. P. Ravikumar
An Euler Path Based Technique for Deadlock-free Multicasting. ICPP (1997)
Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar
Rapid Synthesis of Multi-Chip Systems. VLSI Design (1997)
C. P. Ravikumar, C. S. Panda
Adaptive routing in k-ary n-cubes using incomplete diagnostic information. Microprocess. Microsystems 20 (6) (1997)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
A scheme for multiple on-chip signature checking for embedded SRAMs. ED&TC (1997)
C. P. Ravikumar, Nitin Agrawal, Parul Agarwal
Hierarchical Delay Test Generation. J. Electron. Test. 10 (3) (1997)
C. P. Ravikumar, R. Aggarwal, C. Sharma
A Graph-Theoretic Approach for Register File Based Synthesis. VLSI Design (1997)
C. P. Ravikumar, Tarun Rai, Varun Verma
Kautz graphs as attractive logical topologies in multihop lightwave networks. Comput. Commun. 20 (14) (1997)
R. Parthiban, C. P. Ravikumar, R. Kakarala, J. Sivaswamy
Parallelization of symmetry detection algorithms on a network of workstations. Microprocess. Microsystems 20 (6) (1997)
Ramnik Bajaj, C. P. Ravikumar, Suresh Chandra
Distributed delay constrained multicast path setup algorithm for high speed networks. HiPC (1997)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
Efficient Implementation of Multiple On-Chip Signature Checking. VLSI Design (1997)
C. P. Ravikumar, Rajamani Rajarajan
Genetic Algorithms for Scan Path Design. VLSI Design (1996)
Nidhi Agrawal, C. P. Ravikumar
Fault-tolerant routing in multiply twisted cube topology. J. Syst. Archit. 42 (4) (1996)
C. P. Ravikumar, Augustine R. Thomas, Abhay Gupta
A genetic algorithm for assembling optical computers using faulty optical arrays. HiPC (1996)
C. P. Ravikumar, Vikram Saxena
TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis. VLSI Design 5 (1) (1996)
C. P. Ravikumar, Vikram Saxena
Synthesis of Testable Pipelined Datapaths Using Genetic Search. VLSI Design (1996)
Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar
Efficient Delay Test Generation for Modular Circuits. Great Lakes Symposium on VLSI (1996)
C. P. Ravikumar, R. Aggarwal
Parallel search-and-learn techniques and graph coloring. Knowl. Based Syst. 9 (1) (1996)
Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar
A Novel BIST Architecture With Built-in Self Check. VLSI Design (1996)
C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora
Estimation of Power from Module-level Netlists. VLSI Design (1996)
C. P. Ravikumar, Rajender Sethi
SHARP: A shape recognition system and its parallel implementation. Microprocess. Microsystems 19 (3) (1995)
C. P. Ravikumar, Hemant Joshi
HISCOAP: a hierarchical testability analysis tool. VLSI Design (1995)
C. P. Ravikumar, Naresh Vedi
Heuristic and neural algorithms for mapping tasks to a reconfigurable array. Microprocess. Microprogramming 41 (2) (1995)
C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal
A STAFAN-like functional testability measure for register-level circuits. Asian Test Symposium (1995)
C. P. Ravikumar, G. Manimaran
Star-Graph based multistage interconnection network for ATM switch fabric. SPDP (1994)
C. P. Ravikumar, Haroon Rasheed
TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing. VLSI Design 2 (3) (1994)

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Publication Activity (10 Years)

Top Topics

Top Venues

C. P. Ravikumar