Testability-Driven Layout of Combinational Circuits.

C. P. Ravikumar Nikhil Sharma

Published in: VLSI Design (1998)

Keyphrases

logic circuits
asynchronous circuits
low power
high speed
data driven
circuit design
information retrieval
analog vlsi
tunnel diode
databases
logic synthesis
delay insensitive
power reduction
test data generation
decision trees
social networks
neural network