A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer.
Arasu T. SenthilC. P. RavikumarSoumitra Kumar NandyPublished in: ITC (2005)
Keyphrases
- low power
- low cost
- power consumption
- high speed
- vlsi architecture
- cmos technology
- single chip
- real time
- mixed signal
- low power consumption
- hardware and software
- wireless transmission
- nm technology
- high power
- logic circuits
- digital signal processing
- signal processor
- vlsi circuits
- highly efficient
- cmos image sensor
- delay insensitive
- hardware implementation
- embedded systems
- gate array