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Low-Power Hierarchical Scan Test for Multiple Clock Domains.
Arasu T. Senthil
C. P. Ravikumar
S. K. Nandy
Published in:
J. Low Power Electron. (2007)
Keyphrases
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low power
power consumption
high speed
low cost
single chip
cmos technology
low power consumption
wireless transmission
high power
gate array
multi channel
digital signal processing
vlsi architecture
vlsi circuits