S. K. Nandy

Publication Activity (10 Years)

Years Active: 1986-2022
Publications (10 Years): 40

Top Venues

VLSI Design

CoRR

ARC

IEEE Trans. Parallel Distributed Syst.

Publications

Harish Agrawal, Sumana T., S. K. Nandy
Symmetric Convolutional Filters: A Novel Way to Constrain Parameters in CNN. CoRR (2022)
Pavel G. Emelyanov, Madhava Krishna C, Vadiraj Kulkarni, S. K. Nandy, Denis K. Ponomaryov, Soumyendu Raha
Factorization of Boolean Polynomials: Parallel Algorithms and Experimental Evaluation. Program. Comput. Softw. 47 (2) (2021)
Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy
Towards Accelerated Genome Informatics on Parallel HPC Platforms: The ReneGENE-GI Perspective. J. Signal Process. Syst. 92 (10) (2020)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
Applying Modified Householder Transform to Kalman Filter. VLSI Design (2019)
Ipsita Biswas Mahapatra, S. K. Nandy
EX-DRIVE: An Execution Driven Functional Verification Flow. J. Low Power Electron. 15 (2) (2019)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSI Design (2019)
Vadiraj Kulkarni, Pavel G. Emelyanov, Denis K. Ponomaryov, Madhava Krishna C, Soumyendu Raha, S. K. Nandy
Parallel Factorization of Boolean Polynomials. Ershov Informatics Conference (2019)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design. ARC (2018)
Ipsita Biswas Mahapatra, S. K. Nandy
An Algorithm - Architecture Co-Designed System for Dynamic Execution-Driven Pre-Silicon Verification. ISED (2018)
Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy
ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs. ARC (2018)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR (2018)
Ipsita Biswas Mahapatra, Utkarsh Agarwal, Chandrashekhar Azad, S. K. Nandy
Design Space Exploration of an Execution-Driven Functional Simulation Methodology. VLSI Design (2018)
Santhi Natarajan, N. Krishna Kumar, H. V. Anuchan, Debnath Pal, S. K. Nandy
ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads. ARC (2018)
Mahnaz Mohammadi, Akhil Krishna, Nalesh Sivanandan, S. K. Nandy
A Hardware Architecture for Radial Basis Function Neural Network Classifier. IEEE Trans. Parallel Distributed Syst. 29 (3) (2018)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design. CoRR (2018)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization. IEEE Trans. Parallel Distributed Syst. 29 (8) (2018)
Kavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, Francois Neumann, Philippe Baufreton
™: a case for WCET-friendly hardware accelerators for real time applications (work-in-progress). CASES (2017)
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. Integr. 58 (2017)
Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. Parallel Process. Lett. 27 (3-4) (2017)
Santhi Natarajan, N. Krishna Kumar, Debnath Pal, S. K. Nandy
AccuRA: Accurate alignment of short reads on scalable reconfigurable accelerators. SAMOS (2016)
Gopinath Mahale, Hamsika Mahale, S. K. Nandy, Ranjani Narayan
REFRESH: REDEFINE for Face Recognition Using SURE Homogeneous Cores. IEEE Trans. Parallel Distributed Syst. 27 (12) (2016)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design. CoRR (2016)
Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. VLSI Design (2016)
Mahnaz Mohammadi, Rohit Ronge, Sanjay S. Singapuram, S. K. Nandy
Performance Evaluation of Feed-Forward Backpropagation Neural Network for Classification on a Reconfigurable Hardware Architecture. ARC (2016)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. VLSI Design (2016)
Farhad Merchant, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design. CoRR (2016)
Arnab Kumar Biswas, S. K. Nandy
Role based shared memory access control mechanisms in NoC based MP-SoC. Nano Commun. Networks 7 (2016)
Kavitha T. Madhu, Anuj Rao, Saptarsi Das, Krishna C. Madhava, S. K. Nandy, Ranjani Narayan
Flexible resource allocation and management for application graphs on ReNÉ MPSoC. PARMA-DITAM@HiPEAC (2016)
Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR (2016)
Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. VLSI Design (2016)
Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya
A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks. VLSI Design (2015)
Alexander Fell, S. K. Nandy, Ranjani Narayan
A deterministic, minimal routing algorithm for a toroidal, rectangular honeycomb topology using a 2-tupled relative address. SoCC (2015)
Arnab Kumar Biswas, S. K. Nandy, Ranjani Narayan
Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat. Circuits Syst. Signal Process. 34 (10) (2015)
Vaibhav Ankush Kachore, J. Lakshmi, S. K. Nandy
Location Obfuscation for Location Data Privacy. SERVICES (2015)
Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Compiling HPC Kernels for the REDEFINE CGRA. HPCC/CSS/ICESS (2015)
Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan
Hardware Solution for Real-Time Face Recognition. VLSI Design (2015)
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11 (3) (2015)
Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan
Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array. iNIS (2015)
Pratima Ashok Dhuldhule, J. Lakshmi, S. K. Nandy
High Performance Computing Cloud - A Platform-as-a-Service Perspective. CCBD (2015)
Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna C, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations. VLSI Design (2015)
Gopinath Mahale, Hamsika Mahale, Rajesh Babu Parimi, S. K. Nandy, S. Bhattacharya
Hardware architecture of bi-cubic convolution interpolation for real-time image scaling. FPT (2014)
Kavitha T. Madhu, Saptarsi Das, Madhava Krishna C, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath. ICSAMOS (2014)
Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay
Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. VLSI-SoC (2014)
Aakriti Gupta, J. Lakshmi, S. K. Nandy
Real Time Routing in Road Networks. BDCloud (2014)
Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan
Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR). VLSI Design (2014)
Mahesh Mahadurkar, Farhad Merchant, Arka Maity, Kapil Vatwani, Ishan Munje, Nandhini Gopalan, S. K. Nandy, Ranjani Narayan
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs. ICSAMOS (2014)
S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED (2014)
Saptarsi Das, Kavitha T. Madhu, Madhav Krishna, Nalesh Sivanandan, Farhad Merchant, Santhi Natarajan, Ipsita Biswas, Adithya Pulli, S. K. Nandy, Ranjani Narayan
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths. J. Syst. Archit. 60 (7) (2014)
Pavan Kumar Akulakrishna, J. Lakshmi, S. K. Nandy
Efficient Storage of Big-Data for Real-Time GPS Applications. BDCloud (2014)
Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. ASAP (2014)
S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS (2013)
Mohit Dhingra, J. Lakshmi, S. K. Nandy, Chiranjib Bhattacharyya, Kanchi Gopinath
Elastic Resources Framework in IaaS, Preserving Performance SLAs. IEEE CLOUD (2013)
Ankit Anand, J. Lakshmi, S. K. Nandy
Virtual Machine Placement Optimization Supporting Performance SLAs. CloudCom (1) (2013)
Abhijit Giri, S. K. Nandy
Optimal Pipeline Depth and Supply Voltage for Power-constrained Processors. VLSI Design (2013)
Mohit Dhingra, J. Lakshmi, S. K. Nandy
Resource Usage Monitoring in Clouds. GRID (2012)
Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy
A Method for Flexible Reduction over Binary Fields using a Field Multiplier. SECRYPT (2011)
Adarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere
USHA: Unified software and hardware architecture for video decoding. SASP (2011)
Alok Baluni, Farhad Merchant, S. K. Nandy, Srinivasan Balakrishnan
A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support. ISED (2011)
Ratna Krishnamoorthy, Masahiro Fujita, Keshavan Varadarajan, S. K. Nandy
Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture. FPT (2011)
Ratna Krishnamoorthy, Keshavan Varadarajan, Masahiro Fujita, Mythri Alle, S. K. Nandy, Ranjani Narayan
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. ARC (2011)
J. Lakshmi, S. K. Nandy
I/O Virtualization Architecture for Security. CIT (2010)
Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS (2010)
Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI (2010)
Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita
Towards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE. CASES (2010)
N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture. ICSAMOS (2010)
Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC (2009)
Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES (2009)
J. Lakshmi, S. K. Nandy
I/O Device Virtualization in the Multi-core era, a QoS Perspective. GPC Workshops (2009)
A. N. Satrawala, S. K. Nandy
RETHROTTLE: Execution throttling in the REDEFINE SoC architecture. ICSAMOS (2009)
Ganesh Garga, David Guevorkian, S. K. Nandy, H. S. Jamadagni
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures. ICSAMOS (2009)
Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan
REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9 (2) (2009)
Ritesh Rajore, S. K. Nandy, H. S. Jamadagni
Architecture of Run-Time Reconfigurable Channel Decoder. ICC (2009)
Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy, Ranjani Narayan
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures. ARC (2009)
Adarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, Sreeramula Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan
An Input Triggered Polymorphic ASIC for H.264 Decoding. ASAP (2009)
Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy
Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. ASAP (2008)
Ganesh Garga, Mythri Alle, Keshavan Varadarajan, S. K. Nandy, H. S. Jamadagni
Realizing a flexible constraint length Viterbi decoder for software radio on a de Bruijn interconnection network. SoC (2008)
Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy, Ranjani Narayan
Synthesis of application accelerators on Runtime Reconfigurable Hardware. ASAP (2008)
Joseph Nimmy, C. Ramesh Reddy, Keshavan Varadarajan, Mythri Alle, Alexander Fell, S. K. Nandy, Ranjani Narayan
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router. ASAP (2008)
Adarsha Rao, Mythri Alle, S. K. Nandy, Ranjani Narayan
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders. ASAP (2008)
Subhasis Banerjee, G. Surendra, S. K. Nandy
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation. J. Syst. Archit. 54 (8) (2008)
A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures. FPL (2007)
Subhasis Banerjee, G. Surendra, S. K. Nandy
Program Phase Directed Dynamic Cache Way Reconfiguration for Power Efficiency. ASP-DAC (2007)
Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy
Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electron. 3 (1) (2007)
K. Kalapriya, S. K. Nandy
On the Implementation of a Streaming Video over Peer to Peer network using Middleware Components. ICN/ICONS/MCL (2006)
Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. MICRO (2006)
Mythri Alle, Jayanta Biswas, S. K. Nandy
High Performance VLSI Architecture Design for H.264 CAVLC Decoder. ASAP (2006)
K. Kalapriya, S. K. Nandy, Nanjangud C. Narendra
A Framework for Measurement of End-To-End Qos Requirements in Loosely Coupled Systems. AINA (2) (2006)
J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan
Framework for Enabling Highly Available Distributed Applications for Utility Computing. ISPA (2006)
G. Surendra, Subhasis Banerjee, S. K. Nandy
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations. J. Embed. Comput. 2 (1) (2006)
Raghu Anantharangachar, Gorur N. Shrinivas, S. K. Nandy
Towards Self-Composing, Prioritized and Consequential Services. IEEE SCC (2006)
Sandeep B. Singh, Jayanta Biswas, S. K. Nandy
A Cost Effective Pipelined Divider for Double Precision Floating Point Number. ASAP (2006)
K. C. Nainwal, J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan
A Framework for QoS Adaptive Grid Meta Scheduling. DEXA Workshops (2005)
Nanjangud C. Narendra, Umesh Bellur, S. K. Nandy, K. Kalapriya
Functional and architectural adaptation in pervasive computing environments. MPAC (2005)
K. Kalapriya, S. K. Nandy
Throughput Driven, Highly Available Streaming Stored Playback Video Service over a Peer-to-Peer Network. AINA (2005)
G. Surendra, Subhasis Banerjee, S. K. Nandy
On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort. WMPI (2004)
G. Surendra, Subhasis Banerjee, S. K. Nandy
Power-performance trade-off using pipeline delays. ASP-DAC (2004)
K. Kalapriya, S. K. Nandy, Deepti Srinivasan, R. Uma Maheshwari, V. Satish
A framework for resource discovery in pervasive computing for mobile aware task execution. Conf. Computing Frontiers (2004)
Subhasis Banerjee, G. Surendra, S. K. Nandy
Exploiting program execution phases to trade power and performance for media workload. ASP-DAC (2004)
K. Kalapriya, S. K. Nandy, K. Venkatesh Babu
Can Streaming Of Stored Playback Video Be Supported On Peer to Peer Infrastructure? AINA (2) (2004)
K. Kalapriya, S. K. Nandy, V. Satish, R. Uma Maheshwari, Deepti Srinivas
An Architectural View of the Entities Required for Execution of Task in Pervasive Space. FTDCS (2004)

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Publication Activity (10 Years)

Top Topics

Top Venues

S. K. Nandy