Prasenjit Biswas

Publication Activity (10 Years)

Years Active: 1983-2020
Publications (10 Years): 4

Top Topics

Protein Folding

Annealing Algorithm

Reactive Systems

Health Information

Top Venues

FIRE (Working Notes)

Publications

Prasenjit Biswas, Sarit Pal, Sunil P. Khatri
A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking. ICICT (2020)
Prasenjit Biswas, D. M. H. Walker
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. VLSI Design (2017)
Kamal Sarkar, Debanjan Das, Indra Banerjee, Mamta Kumari, Prasenjit Biswas
JU_KS_Group@FIRE 2016: Consumer Health Information Search. CoRR (2016)
Kamal Sarkar, Debanjan Das, Indra Banerjee, Mamta Kumari, Prasenjit Biswas
JU_KS_Group@FIRE 2016: Consumer Health Information Search. FIRE (Working Notes) (2016)
Prasenjit Biswas, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform. ICSAMOS (2010)
Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. ISVLSI (2010)
Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. SoCC (2009)
Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. CASES (2009)
Mythri Alle, Keshavan Varadarajan, Alexander Fell, C. Ramesh Reddy, Joseph Nimmy, Saptarsi Das, Prasenjit Biswas, Jugantor Chetia, Adarsha Rao, S. K. Nandy, Ranjani Narayan
REDEFINE: Runtime reconfigurable polymorphic ASIC. ACM Trans. Embed. Comput. Syst. 9 (2) (2009)
Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama
SH-5: The 64-Bit SuperH Architecture. IEEE Micro 20 (4) (2000)
Prasenjit Biswas, Andy Freeman, Kouji Yamada, Norio Nakagawa, Kunio Uchiyama
Functional verification of the superscalar SH-4 microprocessor. COMPCON (1997)
Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas
SH3: high code density, low power. IEEE Micro 15 (6) (1995)
Surapong Auwatanamongkol, Andrzej Ciepielewski, Prasenjit Biswas
Cut and Side-Effects in a Data-Driven Implementation of Prolog. New Gener. Comput. 12 (3) (1994)
Dagung Lu, Prasenjit Biswas
An extended scheduling technique for software pipelining. Microprocess. Microprogramming 37 (1-5) (1993)
Behrooz A. Shirazi, Krishna M. Kavi, Ali R. Hurson, Prasenjit Biswas
PARSA: A Parallel Program Scheduling and Assessment Environment. ICPP (2) (1993)
Syhy-Chang Su, Prasenjit Biswas
A memory-mapped interprocessor communication architecture using FIFO RAMs. Microprocess. Microprogramming 34 (1-5) (1992)
Gautam Dewan, Prasenjit Biswas
A snooping cache coherency protocol for hierarchically organized multiprocessors. Microprocessing and Microprogramming 31 (1-5) (1991)
Surapong Auwatanamongkol, Prasenjit Biswas
A Hybrid Architecture and Adaptive Scheduling for Parallel Execution of Logic Programs. ICPP (1) (1991)
Shyh-Chang Su, Prasenjit Biswas
Scheduling demand-driven parallel logic programs on transputers. Microprocessing and Microprogramming 28 (1-5) (1990)
Prasenjit Biswas, Jin Chen
A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machines. Microprocessing and Microprogramming 28 (1-5) (1990)
Chin-Feng Fan, Prasenjit Biswas
Abstract machine LORAP II and experiments in process grain size determination for parallel execution of logic programs. TAI (1989)
Prasenjit Biswas, Shyh-Chang Su, David Y. Y. Yun
A Scalable Abstract Machine Model to Support Limited-OR (LOR) / Restricted-AND Parallelism (RAP) in Logic Programs. ICLP/SLP (1988)
Chien-Chao Tseng, Prasenjit Biswas
A Data-Driven Parallel Execution Model for Logic Programs. ICLP/SLP (1988)
Prasenjit Biswas, Chien-Chao Tseng
LogDf: A Data-Driven Abstract Machine Model for Parallel Execution of Logic Programs. FGCS (1988)
Prasenjit Biswas, Arun K. Majumdar
A Fuzzy Hybrid Model for Pattern Classification. Pattern Recognition (1988)
Prasenjit Biswas, Subrata Dasgupta
Architectural support for variable addressing in Ada - A design approach. Int. J. Parallel Program. 14 (1) (1985)
Prasenjit Biswas, Arun K. Majumdar
A supervised learning algorithm for hierarchical classification of fuzzy patterns. Inf. Sci. 31 (2) (1983)