D. M. H. Walker

Publication Activity (10 Years)

Years Active: 1986-2020
Publications (10 Years): 6

Top Topics

Pattern Generation

Top Venues

J. Electron. Test.

Publications

Avijit Chakraborty, D. M. H. Walker
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. DFT (2020)
Prasenjit Biswas, D. M. H. Walker
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. VLSI Design (2017)
Avijit Chakraborty, D. M. H. Walker
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. ACM Great Lakes Symposium on VLSI (2015)
Tengteng Zhang, D. M. H. Walker
Impact of test compression on power supply noise control. DFTS (2015)
Tengteng Zhang, Yukun Gao, D. M. H. Walker
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. J. Electron. Test. 31 (1) (2015)
Yukun Gao, Tengteng Zhang, Punj Pokharel, Swati Chakraborty, D. M. H. Walker
Pseudo Functional Path Delay Test through Embedded Memories. J. Electron. Test. 31 (1) (2015)
Yukun Gao, Tengteng Zhang, Swati Chakraborty, D. M. H. Walker
Delay Test of Embedded Memories. NATW (2014)
Tengteng Zhang, Yukun Gao, D. M. H. Walker
Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise. NATW (2014)
Kun Bian, D. M. H. Walker, Sunil P. Khatri
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. VLSI Design (2014)
Kun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri
Mixed structural-functional path delay test generation and compaction. DFTS (2013)
Dibakar Gope, D. M. H. Walker
Maximizing crosstalk-induced slowdown during path delay test. ICCD (2012)
Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker
Levelized low cost delay test compaction considering IR-drop induced power supply noise. VTS (2011)
D. M. H. Walker
Challenges in Delay Testing of Integrated Circuits. DFT (2009)
Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integr. 41 (3) (2008)
Zheng Wang, D. M. H. Walker
Dynamic Compaction for High Quality Delay Test. VTS (2008)
Sagar S. Sabade, D. M. H. Walker
Estimation of fault-free leakage current using wafer-level spatial information. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger
Power Supply Noise in Delay Testing. ITC (2006)
Hyun Sung Kim, D. M. H. Walker
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits. MTV (2006)
Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore
Comparison of Delay Tests on Silicon. ITC (2006)
Lei Wu, D. M. H. Walker
A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. DFT (2005)
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
Longest-path selection for delay test under process variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (12) (2005)
Bin Xue, D. M. H. Walker
Is IDDQ Test of Microprocessors Feasible? MTV (2005)
Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker
Static Compaction of Delay Tests Considering Power Supply Noise. VTS (2005)
Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
A vector-based approach for power supply noise analysis in test compaction. ITC (2005)
Bin Xue, D. M. H. Walker
test using built-in current sensing of supply line voltage drop. ITC (2005)
Sagar S. Sabade, D. M. H. Walker
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. VTS (2004)
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED (2004)
Sagar S. Sabade, D. M. H. Walker
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. VLSI Design (2004)
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV (2004)
Sagar S. Sabade, D. M. H. Walker
-based test methods: A survey. ACM Trans. Design Autom. Electr. Syst. 9 (2) (2004)
Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS (2004)
Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC (2004)
Sagar S. Sabade, D. M. H. Walker
data analysis using neighbor current ratios. J. Syst. Archit. 50 (5) (2004)
Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
Longest path selection for delay test under process variation. ASP-DAC (2004)
Sagar S. Sabade, D. M. H. Walker
CROWNE: Current Ratio Outliers with Neighbor Estimator. DFT (2003)
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
A Circuit Level Fault Model for Resistive Opens and Bridges. VTS (2003)
Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
CodSim -- A Combined Delay Fault Simulator. DFT (2003)
Sagar S. Sabade, D. M. H. Walker
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. VLSI Design (2003)
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. 8 (4) (2003)
Wangqi Qiu, D. M. H. Walker
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. ITC (2003)
Wangqi Qiu, D. M. H. Walker
Testing the Path Delay Faults of ISCAS85 Circuit c6288. MTV (2003)
Sagar S. Sabade, D. M. H. Walker
Use of Multiple IDDQ Test Metrics for Outlier Identification. VTS (2003)
Abhijit Prasad, D. M. H. Walker
Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. DFT (2003)
Sagar S. Sabade, D. M. H. Walker
IDDQ Test: Will It Survive the DSM Challenge? IEEE Des. Test Comput. 19 (5) (2002)
Sagar S. Sabade, D. M. H. Walker
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. DFT (2002)
Sagar S. Sabade, D. M. H. Walker
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. VLSI Design (2002)
Sagar S. Sabade, D. M. H. Walker
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. VTS (2002)
Sagar S. Sabade, D. M. H. Walker
Improved wafer-level spatial analysis for I_DDQ limit setting. ITC (2001)
Hoki Kim, D. M. H. Walker, David Colby
A practical built-in current sensor for I_DDQ testing. ITC (2001)
Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee
An efficient solution to the storage correspondence problem for large sequential circuits. ASP-DAC (2001)
Zoran Stanojevic, D. M. H. Walker
FedEx - a fast bridging fault extractor. ITC (2001)
Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. ITC (2000)
Chul Young Lee, D. M. H. Walker
PROBE: A PPSFP Simulator for Resistive Bridging Faults. VTS (2000)
Byungwoo Choi, D. M. H. Walker
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. VTS (2000)
D. M. H. Walker
Design for Yield and Reliability is MORE Important Than DFT. ITC (1999)
Vijay R. Sar-Dessai, D. M. H. Walker
Resistive bridge fault modeling, simulation and test generation. ITC (1999)
Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. Asian Test Symposium (1999)
Debashis Nayak, D. M. H. Walker
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. VTS (1999)
Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. ITC (1998)
Vijay R. Sar-Dessai, D. M. H. Walker
Accurate Fault Modeling and Fault Simulation of Resistive Bridges. DFT (1998)
Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
. FPGA (1998)
Lan Zhao, D. M. H. Walker, Fabrizio Lombardi
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. IEEE Trans. Computers 47 (10) (1998)
Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker
Fatal Fault Probability Prediction for Array Based Designs. DFT (1996)
Yuyun Liao, D. M. H. Walker
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. ITC (1996)
Yuyun Liao, D. M. H. Walker
Optimal voltage testing for physically-based faults. VTS (1996)
G. M. Luong, D. M. H. Walker
Test Generation for Global Delay Faults. ITC (1996)
Hari Balachandran, D. M. H. Walker
Improvement of SRAM-based failure analysis using calibrated Iddq testing. VTS (1996)
Young-Jun Kwon, D. M. H. Walker
Yiel Learning via Functional Test Data. ITC (1995)
Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly
Accurate yield estimation of circuits with redundancy. DFT (1995)
V. Ramakrishnan, D. M. H. Walker
IC Performance Prediction System. ITC (1995)
D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas
The CDB/HCDB semiconductor wafer representation server. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (2) (1993)
Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly
Estimation of reject ratio in testing of combinatorial circuits. VTS (1993)
D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas
A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. DAC (1991)
D. M. H. Walker, Stephen W. Director
VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)