Wojciech Maly

Publication Activity (10 Years)

Years Active: 1982-2013
Publications (10 Years): 0

Top Topics

Information Exchange

Differential Evolution

Delay Insensitive

Top Venues

Publications

Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD (2013)
Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED (2012)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Wojciech Maly
Vertical slit transistor based integrated circuits (veSTICs): feasibility study. ISPD (2011)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
Performance study of VeSFET-based, high-density regular circuits. ISPD (2010)
Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly
Evaluating yield and testing impact of sub-wavelength lithography. VTS (2010)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Wojciech Maly
Vertical slit transistor based integrated circuits (VeSTICs) paradigm. ISPD (2009)
Marcus Weis, Andrzej Pfitzner, Dominik Kasprowicz, Rainer Emling, Wojciech Maly, Doris Schmitt-Landsiedel
Adder Circuits with Transistors using Independently Controlled Gates. ISCAS (2009)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
Transistor-level layout of high-density regular circuits. ISPD (2009)
Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
Is there always performance overhead for regular fabric? ICCD (2008)
Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey
More Moore: foolish, feasible, or fundamentally different? ICCAD (2008)
Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
OPC-Free and Minimally Irregular IC Design Style. DAC (2007)
Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer
Extracting Defect Density and Size Distributions from Product ICs. IEEE Des. Test Comput. 23 (5) (2006)
Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
Extraction of defect density and size distributions from wafer sort test results. DATE (2006)
Yangdong Steve Deng, Wojciech Maly
2.5D system integration: a design driven system implementation schema. ASP-DAC (2004)
Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC (2004)
Yangdong Deng, Wojciech Maly
Physical Design of the "2.5D" Stacked System. ICCD (2003)
Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
Deformations of IC Structure in Test and Yield Learning. ITC (2003)
Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
Progressive Bridge Identification. ITC (2003)
Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly
Modeling the Economics of Testing: A DFT Perspective. IEEE Des. Test Comput. 19 (1) (2002)
Ronald D. Blanton, John T. Chen, Rao Desineni, Kumar N. Dwarakanath, Wojciech Maly, Thomas J. Vogels
Fault Tuples in Diagnosis of Deep-Submicron Circuits. ITC (2002)
John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC (2001)
Wojciech Maly
IC Design in High-Cost Nanometer-Technologies Era. DAC (2001)
Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, A. Richard Newton, Lawrence T. Pileggi, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli
Limitations and challenges of computer-aided design technology for CMOS VLSI. Proc. IEEE 89 (3) (2001)
Yangdong Deng, Wojciech Maly
Interconnect characteristics of 2.5-D system integration scheme. ISPD (2001)
John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
Enabling Embedded Memory Diagnosis via Test Response Compression. VTS (2001)
Wojciech Maly
Quality of Design from an IC Manufacturing Perspective. ISQED (2001)
Peng Li, Pranab K. Nag, Wojciech Maly
Cost based tradeoff analysis of standard cell designs. SLIP (2000)
Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (2) (1999)
Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
An algorithm for determining repetitive patterns in very large IC layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (4) (1999)
Anne E. Gattiker, Wojciech Maly
Current signatures: application [to CMOS]. ITC (1998)
Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
Design-Manufacturing Interface: Part II - Applications. DATE (1998)
Anne E. Gattiker, Wojciech Maly
Toward understanding "Iddq-only" fails. ITC (1998)
Wojciech Maly
Moore's law and physical design of ICs. ISPD (1998)
Hans T. Heineken, Wojciech Maly
Performance - Manufacturability Tradeoffs in IC Design. DATE (1998)
Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
Design-Manufacturing Interface: Part I - Vision. DATE (1998)
Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas
A pattern matching algorithm for verification and analysis of very large IC layouts. ISPD (1998)
Anne E. Gattiker, Wojciech Maly
Smart Substrate MCMs. J. Electron. Test. 10 (1-2) (1997)
Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
To DFT or Not to DFT? ITC (1997)
Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
Detection of Yield Trends. DFT (1997)
Witold A. Pleskacz, Wojciech Maly
Improved Yield Model for Submicron Domain. DFT (1997)
Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment. ITC (1997)
Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
Behavior and testability preservation under the retiming transformation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (5) (1997)
Anne E. Gattiker, Wojciech Maly
Current Signatures: Application. ITC (1997)
Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
CAD at the Design-Manufacturing Interface. DAC (1997)
Wojciech Maly
The future of IC design, testing, and manufacturing. IEEE Des. Test Comput. 13 (4) (1996)
Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
Design for manufacturability in submicron domain. ICCAD (1996)
Thomas E. Marchok, Wojciech Maly
Modeling the Difficulty of Sequential Automatic Test Pattern Generation. ICCD (1996)
Wojciech Maly
New and Not-So-New Test Challenges of the Next Decade. ITC (1996)
Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
Test: Sensitivity Analysis of Scaling. ITC (1996)
Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker
Fatal Fault Probability Prediction for Array Based Designs. DFT (1996)
Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC (1996)
Wojciech Maly, Charles H. Ouyang, Subhendra Ghosh, Sury Maturi
Detection of an antenna effect in VLSI designs. DFT (1996)
Jitendra Khare, Wojciech Maly, Nathan Tiday
Fault characterization of standard cell libraries using inductive contamination. VTS (1996)
Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
A complexity analysis of sequential ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (11) (1996)
Hans T. Heineken, Wojciech Maly
Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. ICCAD (1996)
Charles H. Ouyang, Witold A. Pleskacz, Wojciech Maly
Extraction of critical areas for opens in large VLSI circuits. DFT (1996)
Anne E. Gattiker, Wojciech Maly
Current signatures [VLSI circuit testing]. VTS (1996)
Jitendra Khare, Wojciech Maly
Inductive Contamination Analysis (ICA) with SRAM Application. ITC (1995)
Thomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski
Complexity of sequential ATPG. ED&TC (1995)
Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
On Test Set Preservation of Retimed Circuits. DAC (1995)
Igor Bubel, Wojciech Maly, Thomas Waas, Pranab K. Nag, Hans Hartmann, Doris Schmitt-Landsiedel, Susanne Griep
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout. DFT (1995)
Pranab K. Nag, Wojciech Maly
Hierarchical extraction of critical area for shorts in very large ICs. DFT (1995)
Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly
Accurate yield estimation of circuits with redundancy. DFT (1995)
Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly
Testability Implications of Performance-Driven Logic Synthesis. IEEE Des. Test Comput. 12 (2) (1995)
Wojciech Maly
Integration of Design, Manufacturing and Testing. ITC (1994)
Anne E. Gattiker, Wojciech Maly
Feasibility Study of Smart Substrate Multichip Modules. ITC (1994)
Wojciech Maly, Derek Feltham, Anne E. Gattiker, Mark D. Hobaugh, Kenneth Backus, Michael E. Thomas
Smart-Substrate Multichip-Module Systems. IEEE Des. Test Comput. 11 (2) (1994)
Wojciech Maly
Cost of Silicon Viewed from VLSI Design Perspective. DAC (1994)
Samir Naik, Frank Agricola, Wojciech Maly
Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing. IEEE Des. Test Comput. 10 (2) (1993)
Wojciech Maly
Prospects for WSI: A Manufacturing Perspective. Computer 25 (4) (1992)
Derek Feltham, Jitendra Khare, Wojciech Maly
Design for testability view on placement and routing. EURO-DAC (1992)
Wojciech Maly, Marek J. Patyra
Design of ICs applying built-in current testing. J. Electron. Test. 3 (4) (1992)
Anne Meixner, Wojciech Maly
Fault Modeling for the Testing of Mixed Integrated Circuits. ITC (1991)
Thomas M. Storey, Wojciech Maly, John Andrews, Myron Miske
Stuck Fault and Current Testing Comparison Using CMOS Chip Test. ITC (1991)
Wojciech Maly
What is Design for Manufacturability (DFM)? (Panel Abstract). DAC (1991)
Wojciech Maly
Improving the Quality of Test Education. ITC (1991)
Wojciech Maly
Current testing. ITC (1990)
Wojciech Maly
Computer-aided design for VLSI circuit manufacturability. Proc. IEEE 78 (2) (1990)
Thomas M. Storey, Wojciech Maly
CMOS Bridging Fault Detection. ITC (1990)
Thomas M. Storey, Wojciech Maly
CMOS bridging fault detection. ITC (1990)
Phil Nigh, Wojciech Maly
Test Generation for Current Testing (CMOS ICs). IEEE Des. Test Comput. 7 (1) (1990)
Phil Nigh, Wojciech Maly
Layout-driven test generation. ICCAD (1989)
Wojciech Maly, Samir B. Naik
Process Monitoring Oriented IC Testing. ITC (1989)
Wojciech Maly, Pranab K. Nag, Phil Nigh
Testing oriented analysis of CMOS ICs with opens. ICCAD (1988)
Derek Feltham, Phil Nigh, L. Richard Carley, Wojciech Maly
Current sensing for built-in testing of CMOS circuits. ICCD (1988)
Wojciech Maly, Phil Nigh
Built-in current testing-feasibility study. ICCAD (1988)
Wojciech Maly
Realistic Fault Modeling for VLSI Testing. DAC (1987)
Wojciech Maly, Andrzej J. Strojwas, Stephen W. Director
VLSI Yield Prediction and Estimation: A Unified Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (1) (1986)
Wojciech Maly
Optimal order of the VLSI IC testing sequence. DAC (1986)
Wojciech Maly
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 (3) (1985)
Wojciech Maly, Zygmunt Pizlo
Tolerance Assignment for IC Selection Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4 (2) (1985)
John Paul Shen, Wojciech Maly, F. Joel Ferguson
Inductive Fault Analysis of MOS Integrated Circuits. IEEE Des. Test 2 (6) (1985)
Wojciech Maly, F. Joel Ferguson, John Paul Shen
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells. ITC (1984)
Wojciech Maly, Andrzej J. Strojwas
Statistical Simulation of the IC Manufacturing Process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1 (3) (1982)