Rohit Kapur

Publication Activity (10 Years)

Years Active: 1991-2021
Publications (10 Years): 10

Top Topics

Diagnostic Tests

Fault Diagnosis

Hyperspectral Image Compression

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Pralhadrao V. Shantagiri, Rohit Kapur, Chandrasekar Shastry
New scan compression approach to reduce the test data volume. IET Comput. Digit. Tech. 15 (4) (2021)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Pralhadrao V. Shantagiri, Rohit Kapur
Handling Unknown with Blend of Scan and Scan Compression. J. Electron. Test. 34 (2) (2018)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits. CoRR (2018)
Kanad Basu, Rishi Kumar, Santosh Kulkarni, Rohit Kapur
Deterministic Shift Power Reduction in Test Compression. VDAT (2017)
Subhadip Kundu, Kuldip Kumar, Rishi Kumar, Rohit Kapur
Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test set. ITC (2017)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
Enhancing security of logic encryption using embedded key generation unit. ITC-Asia (2017)
Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta
A New Logic Encryption Strategy Ensuring Key Interdependency. VLSI Design (2017)
Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Small Test Set Generation with High Diagnosability. J. Circuits Syst. Comput. 25 (4) (2016)
Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur
Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors. ITC (2016)
Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur
Fault diagnosis in designs with extreme low pin test data compressors. DATE (2015)
Anshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur
Designing efficient combinational compression architecture for testing industrial circuits. VDAT (2015)
Subramanian Chebiyam, Anshuman Chandra, Rohit Kapur
Designing effective scan compression solutions for industrial circuits. ISQED (2015)
Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
GA based diagnostic test pattern generation for transition faults. VDAT (2015)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Rohit Kapur, Irith Pomeranz
Innovative practices session 10C: Advances in DFT and compression. VTS (2014)
Swapnil Bahl, Shreyans Rungta, Shray Khullar, Rohit Kapur, Anshuman Chandra, Salvatore Talluto, Pramod Notiyath, Ajay Rajagopalan
Unifying scan compression. DFT (2014)
Anshuman Chandra, Subramanian Chebiyam, Rohit Kapur
A Case Study on Implementing Compressed DFT Architecture. ATS (2014)
Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Aggresive scan chain masking for improved diagnosis of multiple scan chain failures. ETS (2013)
Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
A Metric for Test Set Characterization and Customization Toward Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
An ATE assisted DFD technique for volume diagnosis of scan chains. DAC (2013)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. VLSI Design (2012)
Jyotirmoy Saikia, Pramod Notiyath, Santosh Kulkarni, Ashok Anbalan, Rajesh Uppuluri, Tammy Fernandes, Parthajit Bhattacharya, Rohit Kapur
Predicting Scan Compression IP Configurations for Better QoR. Asian Test Symposium (2011)
Uzair Shah Syed, Krishnendu Chakrabarty, Anshuman Chandra, Rohit Kapur
3D-Scalable Adaptive Scan (3D-SAS). 3DIC (2011)
Xiaoqing Wen, Mohammad Tehranipoor, Rohit Kapur, Anand Bhat, Amitava Majumdar, LeRoy Winemberg
Special session 5B: Panel How much toggle activity should we be testing with? VTS (2011)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. VLSI Design (2011)
Anshuman Chandra, Jyotirmoy Saikia, Rohit Kapur
Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C). Asian Test Symposium (2011)
Rohit Kapur
Conference Reports. IEEE Des. Test Comput. 27 (3) (2010)
Rohit Kapur
Conference Reports. IEEE Des. Test Comput. 27 (4) (2010)
Rohit Kapur
Conference Reports. IEEE Des. Test Comput. 27 (2) (2010)
Anshuman Chandra, Yasunari Kanzawa, Rohit Kapur
Proactive management of X's in scan chains for compression. ISQED (2009)
Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller
CTL and Its Usage in the EDA Industry. IEEE Des. Test Comput. 26 (1) (2009)
Anshuman Chandra, Rohit Kapur, Yasunari Kanzawa
Scalable Adaptive Scan (SAS). DATE (2009)
Anshuman Chandra, Felix Ng, Rohit Kapur
Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction. DATE (2008)
Srinivasulu Alampally, Jais Abraham, Rubin A. Parekhji, Rohit Kapur, Thomas W. Williams
Evaluation of Entropy Driven Compression Bounds on Industrial Designs. ATS (2008)
Anshuman Chandra, Rohit Kapur
Interval Based X-Masking for Scan Compression Architectures. ISQED (2008)
Rohit Kapur, Subhasish Mitra, Thomas W. Williams
Historical Perspective on Scan Compression. IEEE Des. Test Comput. 25 (2) (2008)
Anshuman Chandra, Rohit Kapur
Not All Xs are Bad for Scan Compression. ATS (2008)
Anshuman Chandra, Rohit Kapur
Bounded Adjacent Fill for Low Capture Power Scan Testing. VTS (2008)
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
Testing in the year 2020. DATE (2007)
Rohit Kapur, Jindrich Zejda, Thomas W. Williams
Fundamentals of timing information for test: How simple can we get? ITC (2007)
Maria Gkatziani, Rohit Kapur, Qing Su, Ben Mathew, Roberto Mattiuzzo, Laura Tarantini, Cy Hay, Salvatore Talluto, Thomas W. Williams
Accurately Determining Bridging Defects from Layout. DDECS (2007)
Anshuman Chandra, Haihua Yan, Rohit Kapur
Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction. VTS (2007)
Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri
DFT MAX and Power. J. Low Power Electron. 3 (2) (2007)
Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
Minimizing the Impact of Scan Compression. VTS (2007)
Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
OCI: Open Compression Interface. ITC (2006)
Rohit Kapur
Test the test experts: do we know what we are doing? ITC (2005)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur
Efficient compression of deterministic patterns into multiple PRPG seeds. ITC (2005)
Nodari Sitchinava, Samitha Samaranayake, Rohit Kapur, Emil Gizdarski, Frederic Neuveux, Thomas W. Williams
Changing the Scan Enable during Shift. VTS (2004)
Rohit Kapur
Security vs. Test Quality: Are they mutually exclusive? ITC (2004)
Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur
Overview of the IEEE P1500 Standard. ITC (2003)
Samitha Samaranayake, Emil Gizdarski, Nodari Sitchinava, Frederic Neuveux, Rohit Kapur, Thomas W. Williams
A Reconfigurable Shared Scan-in Architecture. VTS (2003)
Bruce Cory, Rohit Kapur, Bill Underwood
Speed Binning with Path Delay Test in 150-nm Technology. IEEE Des. Test Comput. 20 (5) (2003)
Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. DATE (2003)
Nahmsuk Oh, Rohit Kapur, Thomas W. Williams
Fast seed computation for reseeding shift register in test pattern compression. ICCAD (2002)
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
Enhancing test efficiency for delay fault testing using multiple-clocked schemes. DAC (2002)
Samitha Samaranayake, Nodari Sitchinava, Rohit Kapur, Minesh B. Amin, Thomas W. Williams
Dynamic Scan: Driving Down the Cost of Test. Computer 35 (10) (2002)
Loïs Guiller, Frederic Neuveux, S. Duggirala, R. Chandramouli, Rohit Kapur
Integrating DFT in the Physical Synthesis Flow. ITC (2002)
Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. ITC (2002)
Rohit Kapur, Thomas W. Williams, M. Ray Mercer
Directed-Binary Search in Logic BIST Diagnostics. DATE (2002)
Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian
On IEEE P1500's Standard for Embedded Core Test. J. Electron. Test. 18 (4-5) (2002)
Rohit Kapur, Thomas W. Williams
Manufacturing Test of SoCs. Asian Test Symposium (2002)
Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir
A new methodology for improved tester utilization. ITC (2001)
Rohit Kapur, Thomas W. Williams
Tester retargetable patterns. ITC (2001)
Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay
CTL the language for describing core-based test. ITC (2001)
Rohit Kapur, R. Chandramouli, Thomas W. Williams
Strategies for Low-Cost Test. IEEE Des. Test Comput. 18 (6) (2001)
Dwayne Burek, Garen Darbinyan, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti
IP and Automation to Support IEEE P1500. VTS (2001)
Yervant Zorian, Erik Jan Marinissen, Rohit Kapur
On using IEEE P1500 SECT for test plug-n-play. ITC (2000)
Farhad Hayat, Thomas W. Williams, Rohit Kapur, D. Hsu
DFT closure. Asian Test Symposium (2000)
Rohit Kapur, Cy Hay, Thomas W. Williams
The Mutating Metric for Benchmarking Test. IEEE Des. Test Comput. 17 (3) (2000)
Thomas W. Williams, Rohit Kapur
Design for Testability in Nanometer Technologies; Searching for Quality. ISQED (2000)
Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
Towards a standard for embedded core test: an example. ITC (1999)
Rohit Kapur, Thomas W. Williams
Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction. Computer 32 (11) (1999)
Rohit Kapur
High level ATPG is important and is on its way! ITC (1999)
Magdy S. Abadir, Rohit Kapur
Cost-Driven Ranking of Memory Elements for Partial Intrusion. IEEE Des. Test Comput. 14 (3) (1997)
Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly
Test: Sensitivity Analysis of Scaling. ITC (1996)
Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC (1996)
Rohit Kapur, Edward F. Miller
System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction). Computer 29 (11) (1996)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (8) (1996)
Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams
Design of an Efficient Weighted-Random-Pattern Generation System. ITC (1994)
Jaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams
Limitations in predicting defect level based on stuck-at fault coverage. VTS (1994)
Rohit Kapur, M. Ray Mercer
Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes. IEEE Trans. Computers 41 (12) (1992)
Rohit Kapur, Jaehong Park, M. Ray Mercer
All Tests for a Fault Are Not Equally Valuable for Defect Detection. ITC (1992)
M. Ray Mercer, Rohit Kapur, Don E. Ross
Functional Approaches to Generating Orderings for Efficient Symbolic Representations. DAC (1992)
Kenneth M. Butler, Rohit Kapur, M. Ray Mercer, Don E. Ross
The roles of controllability and observability in design for test. VTS (1992)
Don E. Ross, Kenneth M. Butler, Rohit Kapur, M. Ray Mercer
Fast functional evaluation of candidate OBDD variable orderings. EURO-DAC (1991)
Kenneth M. Butler, Don E. Ross, Rohit Kapur, M. Ray Mercer
Heuristics to Compute Variable Orderings for Efficient Manipulation of Ordered Binary Decision Diagrams. DAC (1991)