Santanu Chattopadhyay

ORCID

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 74

Top Venues

VDAT

ISCAS

Integr.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Ramesh Sambangi, Kanchan Manna, Vinay Chakravarthi Gogineni, Santanu Chattopadhyay, Sudipta Mahapatra
Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Ramesh Sambangi, Arun Sammit Pandey, Kanchan Manna, Sudipta Mahapatra, Santanu Chattopadhyay
Application Mapping Onto Manycore Processor Architectures Using Active Search Framework. IEEE Trans. Very Large Scale Integr. Syst. 31 (6) (2023)
Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta, Debesh K. Das, Bhargab B. Bhattacharya
Easily-Verifiable Design of Non-Scan Sequential Machines for Conformance Checking. VLSID (2022)
Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
A Cellular Automata Guided Finite-State-Machine Watermarking Strategy for IP Protection of Sequential Circuits. IEEE Trans. Emerg. Top. Comput. 10 (2) (2022)
Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta
Conformance Testing for Finite State Machines Guided by Deep Neural Network. J. Circuits Syst. Comput. 31 (9) (2022)
Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay
Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic Encryption. IEEE Trans. Emerg. Top. Comput. 9 (4) (2021)
Prasad Nagabhushanamgari, Vikash Sehwag, Indrajit Chakrabarti, Santanu Chattopadhyay
Embedding delay-based physical unclonable functions in networks-on-chip. IET Circuits Devices Syst. 15 (1) (2021)
Ramesh Sambangi, Hitesh Manghnani, Santanu Chattopadhyay
LPNet: A DNN based latency prediction technique for application mapping in Network-on-Chip design. Microprocess. Microsystems 87 (2021)
Habibur Rahaman, Santanu Chattopadhyay, Indranil Sengupta
A Deep Neural Network Guided Testing Approach for Finite State Machines. ISDCS (2021)
Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya
A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing. ISDCS (2020)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits. IEEE Trans. Circuits Syst. II Express Briefs (3) (2020)
Rajit Karmakar, Santanu Chattopadhyay
Hardware IP Protection Using Logic Encryption and Watermarking. ITC (2020)
Rajit Karmakar, Santanu Chattopadhyay
A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan Access. DATE (2020)
Priyajit Mukherjee, Navonil Chatterjee, Santanu Chattopadhyay
Thermal-aware detour routing in 3D NoCs. J. Parallel Distributed Comput. 144 (2020)
Ajay Khare, Chinmay Patil, Santanu Chattopadhyay
Task mapping and flow priority assignment of real-time industrial applications for network-on-chip based design. Microprocess. Microsystems 77 (2020)
Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection. Integr. 74 (2020)
Rajit Karmakar, Santanu Chattopadhyay
On Securing Scan Obfuscation Strategies Against ScanSAT Attack. ISQED (2020)
Kanchan Manna, Chatla Swami Sagar, Santanu Chattopadhyay, Indranil Sengupta
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems. ACM J. Emerg. Technol. Comput. Syst. 15 (1) (2019)
N. Prasad, Navonil Chatterjee, Santanu Chattopadhyay, Indrajit Chakrabarti
Runtime Mitigation of Packet Drop Attacks in Fault-tolerant Networks-on-Chip. CoRR (2019)
Ajay Khare, Irene Anna Boben, Santanu Chattopadhyay
Enhanced Schedulability via Minimal Routing with Mapping and Priority Assignment for Real-Time Network-on-chip. TENCON (2019)
Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay
A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis. DAC (2019)
Priyajit Mukherjee, Kokil Jain, Santanu Chattopadhyay
Thermal-aware task allocation and scheduling for periodic real-time applications in mesh-based heterogeneous NoCs. Real Time Syst. 55 (4) (2019)
Hillol Maity, Kaushik Khatua, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya
Fault Coverage Enhancement via Weighted Random Pattern Generation in BIST Using a DNN-Driven-PSO Approach. ICIT (2019)
Rajit Karmakar, Santanu Chattopadhyay, Mrityunjoy Chakraborty
Improving Security of Logic Encryption in Presence of Design-for-Testability Infrastructure. ISCAS (2019)
Kaushik Khatua, Hillol Maity, Santanu Chattopadhyay, Indranil Sengupta, Girish Patankar, Parthajit Bhattacharya
A Deep Neural Network Augmented Approach for Fixed Polarity AND-XOR Network Synthesis. TENCON (2019)
N. Prasad, Indrajit Chakrabarti, Santanu Chattopadhyay
An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Rajit Karmakar, Harshit Kumar, Santanu Chattopadhyay
On Finding Suitable Key-Gate Locations In Logic Encryption. ISCAS (2018)
N. Prasad, Priyajit Mukherjee, Santanu Chattopadhyay, Indrajit Chakrabarti
Design and evaluation of ZMesh topology for on-chip interconnection networks. J. Parallel Distributed Comput. 113 (2018)
Raghav Sonavane, Gobburi Sai Kashyap, Santanu Chattopadhyay
Thermal Aware Application Mapping and Frequency Scaling for Mesh-Based Network-On-Chip Design. iSES (2018)
Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay
Reliability-aware application mapping onto mesh based Network-on-Chip. Integr. 62 (2018)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits. CoRR (2018)
Priyajit Mukherjee, Sandeep D'Souza, Santanu Chattopadhyay
Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution. Integr. 60 (2018)
Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay
Task mapping and scheduling for network-on-chip based multi-core platform with transient faults. J. Syst. Archit. 83 (2018)
Ajay Khare, Chinmay Patil, Manikanta Nallamalli, Santanu Chattopadhyay
Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC. VDAT (2018)
Kanchan Manna, Priyajit Mukherjee, Santanu Chattopadhyay, Indranil Sengupta
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design. IEEE Trans. Computers 67 (4) (2018)
Rajit Karmakar, Santanu Chattopadhyay
Temperature and data size trade-off in dictionary based test data compression. Integr. 57 (2017)
Navonil Chatterjee, Suraj Paul, Santanu Chattopadhyay
Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform. ACM Trans. Embed. Comput. Syst. 16 (4) (2017)
Soumya J., K. Niranjan Babu, Santanu Chattopadhyay
Multi-Application Mapping onto a Switch-Based Reconfigurable Network-on-Chip Architecture. J. Circuits Syst. Comput. 26 (11) (2017)
Rajit Karmakar, Santanu Chattopadhyay, Rohit Kapur
Enhancing security of logic encryption using embedded key generation unit. ITC-Asia (2017)
Rajit Karmakar, N. Prasad, Santanu Chattopadhyay, Rohit Kapur, Indranil Sengupta
A New Logic Encryption Strategy Ensuring Key Interdependency. VLSI Design (2017)
Navonil Chatterjee, Suraj Paul, Priyajit Mukherjee, Santanu Chattopadhyay
Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform. J. Syst. Archit. 74 (2017)
Priyajit Mukherjee, Santanu Chattopadhyay
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design. Integr. 58 (2017)
N. Prasad, Rajit Karmakar, Santanu Chattopadhyay, Indrajit Chakrabarti
Runtime mitigation of illegal packet request attacks in Networks-on-Chip. ISCAS (2017)
Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Small Test Set Generation with High Diagnosability. J. Circuits Syst. Comput. 25 (4) (2016)
Srinivasa Shashank Nuthakki, Rajit Karmakar, Santanu Chattopadhyay, Krishnendu Chakrabarty
Optimization of the IEEE 1687 access network for hybrid access schedules. VTS (2016)
Rajit Karmakar, Santanu Chattopadhyay
Thermal-Safe Schedule Generation for System-on-Chip Testing. VLSI Design (2016)
Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta
Thermal-Aware Design and Test Techniques for Two-and Three-Dimensional Networks-on-Chip. ISVLSI (2016)
Navonil Chatterjee, Sheshivardhan Reddy, Shilpa Reddy, Santanu Chattopadhyay
A reliability aware application mapping onto mesh based Network-on-Chip. RAIT (2016)
Priyajit Mukherjee, Santanu Chattopadhyay
An ILP-based floorplan-aware path synthesis technique for Application-Specific NoC design. RAIT (2016)
Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay
A strategy for fault tolerant reconfigurable Network-on-Chip design. VDAT (2016)
Bibhas Ghoshal, Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Kanchan Manna, Shivam Swami, Santanu Chattopadhyay, Indranil Sengupta
Integrated Through-Silicon Via Placement and Application Mapping for 3D Mesh-Based NoC Design. ACM Trans. Embed. Comput. Syst. 16 (1) (2016)
Kanchan Manna, Chatla Swamy Sagar, Santanu Chattopadhyay, Indranil Sengupta
Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs. ISVLSI (2016)
Sandeep D'Souza, Soumya J., Santanu Chattopadhyay
Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels. ACM Trans. Archit. Code Optim. 12 (4) (2016)
Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay, Bijit Kumar Das
A hardware based low temperature solution for VLSI testing using decompressor side masking. ISCAS (2015)
N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti
ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms. iNIS (2015)
Soumya J., Kundan Kumar, Santanu Chattopadhyay
Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes. J. Syst. Archit. 61 (9) (2015)
Rajit Karmakar, Santanu Chattopadhyay
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling. Integr. 50 (2015)
Navonil Chatterjee, Santanu Chattopadhyay
Fault tolerant mesh based Network-on-Chip architecture. ISCAS (2015)
Kanchan Manna, Vadapalli Shanmukha Sri Teja, Santanu Chattopadhyay, Indranil Sengupta
TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning. ISVLSI (2015)
Srinivasa Shashank Nuthakki, Santanu Chattopadhyay, Mrityunjoy Chakraborty
Test set customization for improved fault diagnosis without sacrificing coverage. ISCAS (2015)
Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach. VTS (2015)
Srinivasa Shashank Nuthakki, Santanu Chattopadhyay
An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets. ATS (2015)
Pradip Kumar Sahu, Kanchan Manna, Tapan Shah, Santanu Chattopadhyay
A Constructive Heuristic for Application Mapping onto Mesh Based Network-on-Chip. J. Circuits Syst. Comput. 24 (8) (2015)
Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints. ATS (2015)
Soumya J., Srijan Tiwary, Santanu Chattopadhyay
Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores. J. Syst. Archit. 61 (1) (2015)
Santanu Chattopadhyay
Power- and thermal-aware testing of VLSI circuits and systems. VDAT (2015)
Arpita Dutta, Santanu Chattopadhyay
Particle swarm optimization approach for low temperature BIST. VDAT (2015)
Kanchan Manna, Chakradhar Reddy Veeramreddy, Santanu Chattopadhyay, Indranil Sengupta
Thermal-aware multifrequency network-on-chip testing using particle swarm optimisation. Int. J. High Perform. Syst. Archit. 5 (3) (2015)
Rajit Karmakar, Santanu Chattopadhyay
Thermal-Aware Test Data Compression Using Dictionary Based Coding. VLSI Design (2015)
Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
GA based diagnostic test pattern generation for transition faults. VDAT (2015)
N. Prasad, Santanu Chattopadhyay, Indrajit Chakrabarti
Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip. Microprocess. Microsystems 39 (8) (2015)
Sandeep D'Souza, Soumya J., Santanu Chattopadhyay
A constructive heuristic for application mapping onto an express channel based Network-on-Chip. VDAT (2015)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Navonil Chatterjee, N. Prasad, Santanu Chattopadhyay
A spare link based reliable Network-on-Chip design. VDAT (2014)
Santanu Chattopadhyay
Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and Test. VLSI Design (2014)
Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay
Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model. VDAT (2014)
Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta
Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip. VLSI-SoC (2014)
Navonil Chatterjee, Santanu Chattopadhyay, Kanchan Manna
A spare router based reliable Network-on-Chip design. ISCAS (2014)
Pradip Kumar Sahu, Tapan Shah, Kanchan Manna, Santanu Chattopadhyay
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22 (2) (2014)
Soumya J., Ashish Sharma, Santanu Chattopadhyay
A locally reconfigurable Network-on-Chip architecture and application mapping onto it. VDAT (2014)
Soumya J., Ashish Sharma, Santanu Chattopadhyay
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 7 (2) (2014)
Subhadip Kundu, Aniket Jha, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Pradip Kumar Sahu, Kanchan Manna, Nisarg Shah, Santanu Chattopadhyay
Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip. J. Syst. Archit. 60 (7) (2014)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
Aggresive scan chain masking for improved diagnosis of multiple scan chain failures. ETS (2013)
Pradip Kumar Sahu, Santanu Chattopadhyay
A survey on application mapping strategies for Network-on-Chip design. J. Syst. Archit. 59 (1) (2013)
Soumya J., Santanu Chattopadhyay
Application-Specific Network-on-Chip synthesis with flexible router Placement. J. Syst. Archit. 59 (7) (2013)
Subhadip Kundu, Sankhadeep Pal, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
A Metric for Test Set Characterization and Customization Toward Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (11) (2013)
Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization. VDAT (2013)
Arpita Dutta, Subhadip Kundu, Santanu Chattopadhyay
Thermal Aware Don't Care Filling to Reduce Peak Temperature and Thermal Variance during Testing. Asian Test Symposium (2013)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
An ATE assisted DFD technique for volume diagnosis of scan chains. DAC (2013)
S. Krishna Kumar, Subhadip Kundu, Santanu Chattopadhyay
Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing. Integr. 45 (2) (2012)
Pradip Kumar Sahu, Ashish Sharma, Santanu Chattopadhyay
Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization. ISED (2012)
Tapas Kumar Maiti, Subhadip Kundu, Arpita Dutta, Santanu Chattopadhyay
Confidence Based Power Aware Testing. ISED (2012)
Sambhu Nath Pradhan, Santanu Chattopadhyay
Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. 21 (5) (2012)
A. Mitra, Santanu Chattopadhyay
Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique. IET Comput. Digit. Tech. 6 (6) (2012)
Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur
A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection. VLSI Design (2012)
Rekha Govindaraj, Indranil Sengupta, Santanu Chattopadhyay
An Efficient Technique for Longest Prefix Matching in Network Routers. VDAT (2012)
Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay
Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip. VDAT (2012)
Santanu Kundu, Soumya J., Santanu Chattopadhyay
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router. Microprocess. Microsystems 36 (6) (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Santanu Chattopadhyay