Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures.
Ramesh SambangiKanchan MannaVinay Chakravarthi GogineniSantanu ChattopadhyaySudipta MahapatraPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2024)
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