Sambhu Nath Pradhan

Publication Activity (10 Years)

Years Active: 2008-2023
Publications (10 Years): 24

Top Topics

Finite State Machines

Top Venues

J. Circuits Syst. Comput.

Int. J. Comput. Aided Eng. Technol.

Int. J. Circuit Theory Appl.

Int. J. Embed. Syst.

Publications

Kaushik Das, Sambhu Nath Pradhan
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm. Integr. 91 (2023)
Vivek Kumar Singh, Abhishek Nag, Abhishek Bhattacharjee, Sambhu Nath Pradhan
Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA. J. Circuits Syst. Comput. 32 (7) (2023)
Apangshu Das, Vivek Kumar Singh, Sambhu Nath Pradhan
Shared reduced ordered binary decision diagram-based thermal-aware network synthesis. Int. J. Circuit Theory Appl. 50 (6) (2022)
Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation. J. Electron. Test. 38 (1) (2022)
Vivek Kumar Singh, Abhishek Nag, Sambhu Nath Pradhan
Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks. Int. J. Embed. Syst. 15 (4) (2022)
Abhishek Bhattacharjee, Sambhu Nath Pradhan
NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor. J. Circuits Syst. Comput. 30 (11) (2021)
Koel Datta Purkayastha, Ritesh Kishore Mishra, Arunava Shil, Sambhu Nath Pradhan
IoT Based Design of Air Quality Monitoring System Web Server for Android Platform. Wirel. Pers. Commun. 118 (4) (2021)
Abhishek Bhattacharjee, Dheeraj Kumar Sahu, Sambhu Nath Pradhan
Lookup table-based negative-bias temperature instability effect and leakage power co-optimization using genetic algorithm approach. Int. J. Circuit Theory Appl. 49 (7) (2021)
Kaushik Das, Sambhu Nath Pradhan
Field-programmable gate array-based design for real-time computation of ensemble empirical mode decomposition. Int. J. Circuit Theory Appl. 49 (8) (2021)
Somnath Roy Choudhury, Sambhu Nath Pradhan
An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI. IEEE Access 8 (2020)
Apangshu Das, Yallapragada C. Hareesh, Sambhu Nath Pradhan
NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed-Muller Network Synthesis Using Parallel Tabular Technique. J. Circuits Syst. Comput. 29 (15) (2020)
Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan
Low power transistor level synthesis of finite state machines using a novel dual gating technique. Int. J. Embed. Syst. 13 (4) (2020)
Kaushik Das, Debanjali Nath, Sambhu Nath Pradhan
FPGA and ASIC realisation of EMD algorithm for real-time signal processing. IET Circuits Devices Syst. 14 (6) (2020)
Apangshu Das, Sambhu Nath Pradhan
An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis. Int. J. Interact. Multim. Artif. Intell. 6 (4) (2020)
Kaushik Das, Sambhu Nath Pradhan
An efficient hardware realization of EMD for real-time signal processing applications. Int. J. Circuit Theory Appl. 48 (12) (2020)
Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan
Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique. J. Circuits Syst. Comput. 28 (5) (2019)
Somnath Roy Choudhury, Sambhu Nath Pradhan
DOTFloor-A Diffusion Oriented Time-Improved Floorplanner for Macrocells. IEEE Access 7 (2019)
Priyanka Choudhury, Kanchan Manna, Vivek Rai, Sambhu Nath Pradhan
Thermal-Aware Partitioning and Encoding of Power-Gated FSM. J. Circuits Syst. Comput. 28 (9) (2019)
Ashim Saha, Sambhu Nath Pradhan
Facial expression recognition based on eigenspaces and principle component analysis. Int. J. Comput. Vis. Robotics 8 (2) (2018)
Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan
Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. J. Circuits Syst. Comput. 26 (3) (2017)
Sambhu Nath Pradhan, Priyanka Choudhury, Debanjali Nath
Transistor level realisation of power gated FSM. Int. J. Comput. Aided Eng. Technol. 9 (3) (2017)
Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan
Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. J. Circuits Syst. Comput. 25 (5) (2016)
Apangshu Das, Sambhu Nath Pradhan
Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits. VLSI Design 2016 (2016)
Abhishek Nag, Sambhu Nath Pradhan
An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning. J. Circuits Syst. Comput. 25 (5) (2016)
Priyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan
Thermal aware AND-OR-XOR network synthesis. VDAT (2015)
Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath
Layout-oriented look up table-based dual threshold approach to reduce leakage. Int. J. Comput. Aided Eng. Technol. 7 (4) (2015)
Apangshu Das, Sambhu Nath Pradhan
Thermal aware FPRM based AND-XOR network synthesis of logic circuits. ReTIS (2015)
Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan
Power gating architecture implementation inside clock period to reduce power. Int. J. Comput. Aided Eng. Technol. 6 (3) (2014)
Angshuman Chakraborty, Sambhu Nath Pradhan
Gate level leakage minimisation at 90 nm technology. Int. J. Comput. Aided Eng. Technol. 5 (4) (2013)
Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan
Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). VDAT (2013)
Angshuman Chakraborty, Sambhu Nath Pradhan
A technique for power reduction of CMOS circuit at 65nm technology. RAIT (2012)
Priyanka Choudhury, Sambhu Nath Pradhan
An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together. J. Low Power Electron. 8 (4) (2012)
Sambhu Nath Pradhan, Santanu Chattopadhyay
Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. 21 (5) (2012)
Priyanka Choudhury, Sambhu Nath Pradhan
Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm. VDAT (2012)
Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
Low power finite state machine synthesis using power-gating. Integr. 44 (3) (2011)
Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
And-or-XOR Network Synthesis with Area-Power Trade-Off. J. Circuits Syst. Comput. 20 (6) (2011)
Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. ISVLSI (2008)
Sambhu Nath Pradhan, Santanu Chattopadhyay
AND-XOR Network Synthesis with Area-Power Trade-off. ICIIS (2008)
Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay
Three-level AND-OR-XOR network synthesis: A GA based approach. APCCAS (2008)