Debanjali Nath

Publication Activity (10 Years)

Years Active: 2013-2020
Publications (10 Years): 6

Top Topics

Power Reduction

Multiresolution

Layered Architecture

Top Venues

Int. J. Comput. Aided Eng. Technol.

J. Circuits Syst. Comput.

IET Circuits Devices Syst.

Publications

Kaushik Das, Debanjali Nath, Sambhu Nath Pradhan
FPGA and ASIC realisation of EMD algorithm for real-time signal processing. IET Circuits Devices Syst. 14 (6) (2020)
Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan
Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. J. Circuits Syst. Comput. 26 (3) (2017)
Sambhu Nath Pradhan, Priyanka Choudhury, Debanjali Nath
Transistor level realisation of power gated FSM. Int. J. Comput. Aided Eng. Technol. 9 (3) (2017)
Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan
Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. J. Circuits Syst. Comput. 25 (5) (2016)
Priyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan
Thermal aware AND-OR-XOR network synthesis. VDAT (2015)
Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath
Layout-oriented look up table-based dual threshold approach to reduce leakage. Int. J. Comput. Aided Eng. Technol. 7 (4) (2015)
Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan
Power gating architecture implementation inside clock period to reduce power. Int. J. Comput. Aided Eng. Technol. 6 (3) (2014)
Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan
Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). VDAT (2013)