Abhishek Nag

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 7

Top Topics

Finite State Machines

Functional Decomposition

Top Venues

J. Circuits Syst. Comput.

Int. J. Embed. Syst.

Int. J. Comput. Aided Eng. Technol.

J. Electron. Test.

Publications

Vivek Kumar Singh, Abhishek Nag, Abhishek Bhattacharjee, Sambhu Nath Pradhan
Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA. J. Circuits Syst. Comput. 32 (7) (2023)
Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation. J. Electron. Test. 38 (1) (2022)
Vivek Kumar Singh, Abhishek Nag, Sambhu Nath Pradhan
Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks. Int. J. Embed. Syst. 15 (4) (2022)
Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan
Low power transistor level synthesis of finite state machines using a novel dual gating technique. Int. J. Embed. Syst. 13 (4) (2020)
Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan
Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique. J. Circuits Syst. Comput. 28 (5) (2019)
Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan
Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. J. Circuits Syst. Comput. 26 (3) (2017)
Abhishek Nag, Sambhu Nath Pradhan
An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning. J. Circuits Syst. Comput. 25 (5) (2016)
Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath
Layout-oriented look up table-based dual threshold approach to reduce leakage. Int. J. Comput. Aided Eng. Technol. 7 (4) (2015)
Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan
Power gating architecture implementation inside clock period to reduce power. Int. J. Comput. Aided Eng. Technol. 6 (3) (2014)