Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation.
Abhishek BhattacharjeeAbhishek NagKaushik DasSambhu Nath PradhanPublished in: J. Electron. Test. (2022)
Keyphrases
- power dissipation
- power consumption
- power reduction
- low power
- clock gating
- cmos technology
- power saving
- chip design
- logic circuits
- nm technology
- energy efficiency
- user interface
- low cost
- design process
- data transmission
- digital signal processing
- computing systems
- neural network
- image analysis
- relational databases
- case study
- image processing