A technique for power reduction of CMOS circuit at 65nm technology.

Angshuman Chakraborty Sambhu Nath Pradhan

Published in: RAIT (2012)

Keyphrases

nm technology
power reduction
power consumption
power dissipation
low power
power saving
high speed
energy efficiency
cmos technology
digital signal processing
low cost
energy saving
fine grained
image processing
user interface
data center