Fault tolerant mesh based Network-on-Chip architecture.

Navonil Chatterjee Santanu Chattopadhyay

Published in: ISCAS (2015)

Keyphrases

fault tolerant
network on chip
interconnection networks
fault tolerance
multi processor
routing algorithm
packet switched
distributed systems
load balancing
network simulator
data transfer
multistage
wireless sensor networks
power consumption
hardware implementation
program execution
data management
real time