A New Test Vector Reordering Technique for Low Power Combinational Circuit Testing.
Hillol MaityKaushik KhatuaSantanu ChattopadhyayIndranil SenguptaGirish PatankarParthajit BhattacharyaPublished in: ISDCS (2020)
Keyphrases
- low power
- logic circuits
- high speed
- power consumption
- low cost
- test cases
- cmos technology
- gate array
- vlsi circuits
- software testing
- single chip
- power reduction
- wireless transmission
- power dissipation
- high power
- test suite
- delay insensitive
- real time
- vlsi architecture
- nm technology
- low power consumption
- digital signal processing
- mixed signal
- digital camera
- feature vectors