Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design.
Priyajit MukherjeeSantanu ChattopadhyayPublished in: Integr. (2017)
Keyphrases
- low power
- low power consumption
- application specific
- low latency
- high speed
- high bandwidth
- power dissipation
- low cost
- power consumption
- single chip
- cmos technology
- network on chip
- general purpose
- real time
- digital signal processing
- ultra low power
- highly efficient
- high throughput
- parallel algorithm
- design process
- cloud computing